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authorAurelien Jarno <aurelien@aurel32.net>2010-12-28 17:46:59 +0100
committerAurelien Jarno <aurelien@aurel32.net>2010-12-31 22:23:38 +0100
commitf96a38347a0c6ab31fbb6200c13e684d1fee449c (patch)
tree61f7f5b8544a44d210927d4521cd55cc9f353c94
parent8aac08b10b2e8c131b9385d2dc37e4a02e1d12c1 (diff)
downloadqemu-arm-f96a38347a0c6ab31fbb6200c13e684d1fee449c.tar.gz
TCG: Improve tb_phys_hash_func()
Most of emulated CPU have instructions aligned on 16 or 32 bits, while on others GCC tries to align the target jump location. This means that 1/2 or 3/4 of tb_phys_hash entries are never used. Update the hash function tb_phys_hash_func() to ignore the two lowest bits of the address. This brings a 6% speed-up when booting a MIPS image. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r--exec-all.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/exec-all.h b/exec-all.h
index 6821b17943..a4b75bdbcb 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -177,7 +177,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
{
- return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
+ return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
}
TranslationBlock *tb_alloc(target_ulong pc);