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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-06-25 22:25:22 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-06-25 22:25:22 +0000
commit9d42037b1d75c8f1b187d0b3187bd7891b909a56 (patch)
treec0ececacf657143654ec8801a1a6232040315b3e
parent2a4188a38fa3a91a9286da6fe077b6218378504d (diff)
support for dynamic address space changes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2021 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--exec.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/exec.c b/exec.c
index 7e6f96688d..dd42f77d8e 100644
--- a/exec.c
+++ b/exec.c
@@ -1779,6 +1779,7 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
{
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
+ CPUState *env;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
end_addr = start_addr + size;
@@ -1789,6 +1790,13 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
(phys_offset & IO_MEM_ROMD))
phys_offset += TARGET_PAGE_SIZE;
}
+
+ /* since each CPU stores ram addresses in its TLB cache, we must
+ reset the modified entries */
+ /* XXX: slow ! */
+ for(env = first_cpu; env != NULL; env = env->next_cpu) {
+ tlb_flush(env, 1);
+ }
}
static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)