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authorRichard Henderson <rth@twiddle.net>2012-03-24 09:51:10 -0700
committerBlue Swirl <blauwirbel@gmail.com>2012-03-24 17:07:28 +0000
commita44a27775af6e745be50b23ae0f0aeb6f8462c80 (patch)
tree0013b3d9086af1dcbb304b71feac6000a1899815
parent4a58aedff479e02c33ba74d752f34944751ba28b (diff)
downloadqemu-arm-a44a27775af6e745be50b23ae0f0aeb6f8462c80.tar.gz
target-alpha: Move fpcr helpers from op_helper.c to helper.c.
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--target-alpha/helper.c14
-rw-r--r--target-alpha/helper.h4
-rw-r--r--target-alpha/op_helper.c10
-rw-r--r--target-alpha/translate.c6
4 files changed, 17 insertions, 17 deletions
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 584457f062..3333bfa1b9 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -159,9 +159,19 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
env->fpcr_undz = (val & FPCR_UNDZ) != 0;
}
+uint64_t helper_load_fpcr(CPUAlphaState *env)
+{
+ return cpu_alpha_load_fpcr(env);
+}
+
+void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
+{
+ cpu_alpha_store_fpcr(env, val);
+}
+
#if defined(CONFIG_USER_ONLY)
-int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, target_ulong address, int rw,
- int mmu_idx)
+int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong address,
+ int rw, int mmu_idx)
{
env->exception_index = EXCP_MMFAULT;
env->trap_arg0 = address;
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index d36df5fb9e..e193c2676e 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -34,8 +34,8 @@ DEF_HELPER_FLAGS_1(pkwb, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
DEF_HELPER_FLAGS_1(unpkbl, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
DEF_HELPER_FLAGS_1(unpkbw, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
-DEF_HELPER_FLAGS_0(load_fpcr, TCG_CALL_CONST | TCG_CALL_PURE, i64)
-DEF_HELPER_FLAGS_1(store_fpcr, TCG_CALL_CONST, void, i64)
+DEF_HELPER_FLAGS_1(load_fpcr, TCG_CALL_CONST | TCG_CALL_PURE, i64, env)
+DEF_HELPER_FLAGS_2(store_fpcr, TCG_CALL_CONST, void, env, i64)
DEF_HELPER_FLAGS_1(f_to_memory, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64)
DEF_HELPER_FLAGS_1(memory_to_f, TCG_CALL_CONST | TCG_CALL_PURE, i64, i32)
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 6711d998b9..59ee31e2f8 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -43,16 +43,6 @@ uint64_t helper_load_pcc (void)
#endif
}
-uint64_t helper_load_fpcr (void)
-{
- return cpu_alpha_load_fpcr (env);
-}
-
-void helper_store_fpcr (uint64_t val)
-{
- cpu_alpha_store_fpcr (env, val);
-}
-
uint64_t helper_addqv (uint64_t op1, uint64_t op2)
{
uint64_t tmp = op1;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index a9b97a3188..6f31b6dbe0 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2678,17 +2678,17 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x024:
/* MT_FPCR */
if (likely(ra != 31))
- gen_helper_store_fpcr(cpu_fir[ra]);
+ gen_helper_store_fpcr(cpu_env, cpu_fir[ra]);
else {
TCGv tmp = tcg_const_i64(0);
- gen_helper_store_fpcr(tmp);
+ gen_helper_store_fpcr(cpu_env, tmp);
tcg_temp_free(tmp);
}
break;
case 0x025:
/* MF_FPCR */
if (likely(ra != 31))
- gen_helper_load_fpcr(cpu_fir[ra]);
+ gen_helper_load_fpcr(cpu_fir[ra], cpu_env);
break;
case 0x02A:
/* FCMOVEQ */