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authorPeter Maydell <peter.maydell@linaro.org>2012-06-07 13:02:28 +0930
committerPeter Maydell <peter.maydell@linaro.org>2012-07-25 13:35:00 +0100
commitdcf438d892f9fbed5595868dc0d4b748cb427304 (patch)
treebeb39b34f6ea4fad70ce83c116f7cee253c15275
parent5b6e60e1afd0719e16bf66f965e954fda37e41f8 (diff)
downloadqemu-arm-dcf438d892f9fbed5595868dc0d4b748cb427304.tar.gz
hw/omap_intc.c: Don't complain about nonexistent register read by Linux
The Linux omap kernel now deliberately reads from the nonexistent register at 0xf8, which only exists on ti816x, because it knows that on omap2 and omap3 this will read as zero. Handle it that way (ie suppress qemu's complaint about read of a bad register), since otherwise the omap3 model has so many warnings it is unusable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/omap_intc.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/omap_intc.c b/hw/omap_intc.c
index 5076e07ed5..4bfd216b63 100644
--- a/hw/omap_intc.c
+++ b/hw/omap_intc.c
@@ -410,7 +410,11 @@ static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
offset &= ~0x60;
bank = &s->bank[bank_no];
} else {
- OMAP_BAD_REG(addr);
+ /* Linux reads the nonexistent interrupt status register at 0xf8
+ * every time through its interrupt handler, so don't actually
+ * warn about it because it swamps the console with output.
+ */
+ /* OMAP_BAD_REG(addr); */
return 0;
}
}