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authorPeter Maydell <peter.maydell@linaro.org>2012-06-07 13:02:28 +0930
committerPeter Maydell <peter.maydell@linaro.org>2012-07-25 13:34:58 +0100
commit5b6e60e1afd0719e16bf66f965e954fda37e41f8 (patch)
tree3ffc66c709673cfc22f212cc8a78ecf9f5dd6c05
parent896a66f012dada4f4de0334cf7354f2b253630e3 (diff)
downloadqemu-arm-5b6e60e1afd0719e16bf66f965e954fda37e41f8.tar.gz
hw/nand: Support cache status bits and read cache commands
TODO: check vs spec, are we just ignoring these commands, is that correct? consider renaming the ready bits On reset, set the Ready bits in the status register (both the original bit 6 and the new bit 5 used by eg the STM NAND chips). Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio <riku.voipio@iki.fi> [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/nand.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/hw/nand.c b/hw/nand.c
index e9501ae038..72d9e97853 100644
--- a/hw/nand.c
+++ b/hw/nand.c
@@ -28,6 +28,9 @@
# define NAND_CMD_READ1 0x01
# define NAND_CMD_READ2 0x50
# define NAND_CMD_LPREAD2 0x30
+# define NAND_CMD_READCACHESTART 0x31
+# define NAND_CMD_READCACHEEXIT 0x34
+# define NAND_CMD_READCACHELAST 0x3f
# define NAND_CMD_NOSERIALREAD2 0x35
# define NAND_CMD_RANDOMREAD1 0x05
# define NAND_CMD_RANDOMREAD2 0xe0
@@ -46,7 +49,7 @@
# define NAND_IOSTATUS_PLANE1 (1 << 2)
# define NAND_IOSTATUS_PLANE2 (1 << 3)
# define NAND_IOSTATUS_PLANE3 (1 << 4)
-# define NAND_IOSTATUS_BUSY (1 << 6)
+# define NAND_IOSTATUS_READY (3 << 5)
# define NAND_IOSTATUS_UNPROTCT (1 << 7)
# define MAX_PAGE 0x800
@@ -231,6 +234,7 @@ static void nand_reset(DeviceState *dev)
s->iolen = 0;
s->offset = 0;
s->status &= NAND_IOSTATUS_UNPROTCT;
+ s->status |= NAND_IOSTATUS_READY;
}
static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
@@ -246,6 +250,7 @@ static void nand_command(NANDFlashState *s)
unsigned int offset;
switch (s->cmd) {
case NAND_CMD_READ0:
+ case NAND_CMD_READCACHEEXIT:
s->iolen = 0;
break;
@@ -479,7 +484,10 @@ void nand_setio(DeviceState *dev, uint32_t value)
NANDFlashState *s = (NANDFlashState *) dev;
if (!s->ce && s->cle) {
if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
- if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
+ if (s->cmd == NAND_CMD_READ0
+ && (value == NAND_CMD_LPREAD2
+ || value == NAND_CMD_READCACHESTART
+ || value == NAND_CMD_READCACHELAST))
return;
if (value == NAND_CMD_RANDOMREAD1) {
s->addr &= ~((1 << s->addr_shift) - 1);
@@ -506,7 +514,8 @@ void nand_setio(DeviceState *dev, uint32_t value)
s->cmd == NAND_CMD_BLOCKERASE2 ||
s->cmd == NAND_CMD_NOSERIALREAD2 ||
s->cmd == NAND_CMD_RANDOMREAD2 ||
- s->cmd == NAND_CMD_RESET)
+ s->cmd == NAND_CMD_RESET ||
+ s->cmd == NAND_CMD_READCACHEEXIT)
nand_command(s);
if (s->cmd != NAND_CMD_RANDOMREAD2) {