aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2012-06-07 13:02:27 +0930
committerPeter Maydell <peter.maydell@linaro.org>2012-07-25 13:34:35 +0100
commit5184cb0a3f03215cd8e1688dcf24610e7542c4be (patch)
treeff506d12f121545acbd4092ed679508e3a78e406
parent6b854ff9138c97c02af88997fcd4677c5243021b (diff)
downloadqemu-arm-5184cb0a3f03215cd8e1688dcf24610e7542c4be.tar.gz
Add Cortex A8 r2 support
-rw-r--r--target-arm/cpu.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8c5e95d6b9..252c9036af 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -427,6 +427,46 @@ static void cortex_a8_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
}
+static void cortex_a8_r2_initfn(Object *obj)
+{
+ /* TODO:
+ * 1. do we really need this?
+ * 2. are these register values all correct? mostly same as A8 currently
+ */
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP3);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);
+ cpu->midr = 0x410fc083;
+ cpu->reset_fpsid = 0x410330c2;
+ cpu->mvfr0 = 0x11110222;
+ cpu->mvfr1 = 0x00011111;
+ cpu->ctr = 0x82048004;
+ cpu->reset_sctlr = 0x00c50078;
+ cpu->id_pfr0 = 0x1031;
+ cpu->id_pfr1 = 0x11;
+ cpu->id_dfr0 = 0x400;
+ cpu->id_afr0 = 0;
+ cpu->id_mmfr0 = 0x31100003;
+ cpu->id_mmfr1 = 0x20000000;
+ cpu->id_mmfr2 = 0x01202000;
+ cpu->id_mmfr3 = 0x11;
+ cpu->id_isar0 = 0x00101111;
+ cpu->id_isar1 = 0x12112111;
+ cpu->id_isar2 = 0x21232031;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x00111142;
+ cpu->clidr = (1 << 27) | (2 << 24) | 3;
+ cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
+ cpu->ccsidr[2] = 0xf03fe03a; /* 256k L2 cache. */
+ cpu->reset_auxcr = 2;
+ define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
+}
+
static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
/* power_control should be set to maximum latency. Again,
* default to 0 and set by private hook
@@ -742,6 +782,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
+ { .name = "cortex-a8-r2",.initfn = cortex_a8_r2_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
{ .name = "ti925t", .initfn = ti925t_initfn },