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authorAlistair Francis <alistair.francis@wdc.com>2022-06-09 09:47:01 +1000
committerAlistair Francis <alistair.francis@wdc.com>2022-06-10 09:42:12 +1000
commit07314158f6aa4d2589520c194a7531b9364a8d54 (patch)
treef1f508cc436cab122b0d832653b4a27245114597
parent26b2bc58599c02b35e55afbd1bd050faa3d187c2 (diff)
target/riscv: trans_rvv: Avoid assert for RV32 and e64
When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside tcg_gen_gvec_dup_i32(). This patch checks that condition and instead uses tcg_gen_gvec_dup_i64() is required. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028 Suggested-by: Robert Bu <robert.bu@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--target/riscv/insn_trans/trans_rvv.c.inc12
1 files changed, 10 insertions, 2 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4f84d4878a..6c091824b6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2128,8 +2128,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
s1 = get_gpr(s, a->rs1, EXT_SIGN);
if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
- tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), s1);
+ if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
+ TCGv_i64 s1_i64 = tcg_temp_new_i64();
+ tcg_gen_ext_tl_i64(s1_i64, s1);
+ tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1_i64);
+ tcg_temp_free_i64(s1_i64);
+ } else {
+ tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1);
+ }
} else {
TCGv_i32 desc;
TCGv_i64 s1_i64 = tcg_temp_new_i64();