diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-07-15 10:53:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-18 10:59:47 +0100 |
| commit | 8fe612a183dec4c63afdc57537079bc742d024ca (patch) | |
| tree | e67b50f02591b71681d33d2c5ba6964a29776458 | |
| parent | c90df7ce4ef50f9cea3c42daea4fc167bb0d9d2e (diff) | |
target/arm: Remove duplicate 'plus1' function from Neon and SVE decodepull-target-arm-20210718
The Neon and SVE decoders use private 'plus1' functions to implement
"add one" for the !function decoder syntax. We have a generic
"plus_1" function in translate.h, so use that instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210715095341.701-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/neon-ls.decode | 4 | ||||
| -rw-r--r-- | target/arm/neon-shared.decode | 2 | ||||
| -rw-r--r-- | target/arm/sve.decode | 2 | ||||
| -rw-r--r-- | target/arm/translate-neon.c | 5 | ||||
| -rw-r--r-- | target/arm/translate-sve.c | 5 |
5 files changed, 4 insertions, 14 deletions
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode index 0a2a0e15db..c5f364cbc0 100644 --- a/target/arm/neon-ls.decode +++ b/target/arm/neon-ls.decode @@ -41,8 +41,8 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ vd=%vd_dp # Neon load/store single structure to one lane -%imm1_5_p1 5:1 !function=plus1 -%imm1_6_p1 6:1 !function=plus1 +%imm1_5_p1 5:1 !function=plus_1 +%imm1_6_p1 6:1 !function=plus_1 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \ vd=%vd_dp size=0 stride=1 diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index df80e6ebf6..8e6bd0b61f 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -38,7 +38,7 @@ # which is 0 for fp16 and 1 for fp32 into a MO_* constant. # (Note that this is the reverse of the sense of the 1-bit size # field in the 3same_fp Neon insns.) -%vcadd_size 20:1 !function=plus1 +%vcadd_size 20:1 !function=plus_1 VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \ vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a62c169f1a..c60b9f0fec 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -22,7 +22,7 @@ ########################################################################### # Named fields. These are primarily for disjoint fields. -%imm4_16_p1 16:4 !function=plus1 +%imm4_16_p1 16:4 !function=plus_1 %imm6_22_5 22:1 5:5 %imm7_22_16 22:2 16:5 %imm8_16_10 16:5 10:3 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index a45616cb63..c53ab20fa4 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -28,11 +28,6 @@ #include "translate.h" #include "translate-a32.h" -static inline int plus1(DisasContext *s, int x) -{ - return x + 1; -} - static inline int neon_3same_fp_size(DisasContext *s, int x) { /* Convert 0==fp32, 1==fp16 into a MO_* value */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 35d838aa06..bc91a64171 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -70,11 +70,6 @@ static int tszimm_shl(DisasContext *s, int x) return x - (8 << tszimm_esz(s, x)); } -static inline int plus1(DisasContext *s, int x) -{ - return x + 1; -} - /* The SH bit is in bit 8. Extract the low 8 and shift. */ static inline int expand_imm_sh8s(DisasContext *s, int x) { |