diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:15:50 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-21 17:12:50 +0100 |
| commit | 8abd3c80b18757c54e9b270244ca351e407b6405 (patch) | |
| tree | f2d4b5ac0854f398c0059231eb53f116a3c0162f | |
| parent | 249b5309c44831555b7fb6dab68d7a6f9f573882 (diff) | |
target/arm: Implement MVE VMVN (register)
Implement the MVE VMVN(register) operation. Note that for
predication this operation is byte-by-byte.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-7-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/helper-mve.h | 2 | ||||
| -rw-r--r-- | target/arm/mve.decode | 3 | ||||
| -rw-r--r-- | target/arm/mve_helper.c | 4 | ||||
| -rw-r--r-- | target/arm/translate-mve.c | 5 |
4 files changed, 14 insertions, 0 deletions
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 4c89387587..f1dc52f7a5 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -47,3 +47,5 @@ DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vmvn, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 16ee511a5c..ff8afb682f 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -30,6 +30,7 @@ @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm +@1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0 # Vector loads and stores @@ -74,3 +75,5 @@ VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op + +VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 8b565b50a9..fa0a32d284 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -277,3 +277,7 @@ DO_1OP(vrev32h, 4, uint32_t, hswap32) DO_1OP(vrev64b, 8, uint64_t, bswap64) DO_1OP(vrev64h, 8, uint64_t, hswap64) DO_1OP(vrev64w, 8, uint64_t, wswap64) + +#define DO_NOT(N) (~(N)) + +DO_1OP(vmvn, 8, uint64_t, DO_NOT) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 32a8324c5e..bd908abcff 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -232,3 +232,8 @@ static bool trans_VREV64(DisasContext *s, arg_1op *a) }; return do_1op(s, a, fns[a->size]); } + +static bool trans_VMVN(DisasContext *s, arg_1op *a) +{ + return do_1op(s, a, gen_helper_mve_vmvn); +} |