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authorMatheus Ferst <matheus.ferst@eldorado.org.br>2021-06-01 16:35:26 -0300
committerDavid Gibson <david@gibson.dropbear.id.au>2021-06-03 18:10:31 +1000
commita5f56954c798f81a58f7f68e82143d13bb73509b (patch)
tree70372796e31eb1b868dbf836464601c64cea32c3
parent89ccd7dc3fbce4a46679f282b47789e34fc3528a (diff)
downloadqemu-arm-a5f56954c798f81a58f7f68e82143d13bb73509b.tar.gz
target/ppc: Implement vcfuged instruction
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-13-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
-rw-r--r--target/ppc/insn32.decode7
-rw-r--r--target/ppc/translate.c1
-rw-r--r--target/ppc/translate/vector-impl.c.inc56
3 files changed, 64 insertions, 0 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d4044d9069..77edf407ab 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,9 @@
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+&VX vrt vra vrb
+@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+
+## Vector Bit Manipulation Instruction
+
+VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3c3cb1b664..ed5515f8e2 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7538,6 +7538,7 @@ static int times_4(DisasContext *ctx, int x)
#include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.c.inc"
+#include "translate/vector-impl.c.inc"
#include "translate/dfp-impl.c.inc"
diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
new file mode 100644
index 0000000000..117ce9b137
--- /dev/null
+++ b/target/ppc/translate/vector-impl.c.inc
@@ -0,0 +1,56 @@
+/*
+ * Power ISA decode for Vector Facility instructions
+ *
+ * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ALTIVEC(CTX) \
+ do { \
+ if (unlikely(!(CTX)->altivec_enabled)) { \
+ gen_exception((CTX), POWERPC_EXCP_VPU); \
+ return true; \
+ } \
+ } while (0)
+
+static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 tgt, src, mask;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_ALTIVEC(ctx);
+
+ tgt = tcg_temp_new_i64();
+ src = tcg_temp_new_i64();
+ mask = tcg_temp_new_i64();
+
+ /* centrifuge lower double word */
+ get_cpu_vsrl(src, a->vra + 32);
+ get_cpu_vsrl(mask, a->vrb + 32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrl(a->vrt + 32, tgt);
+
+ /* centrifuge higher double word */
+ get_cpu_vsrh(src, a->vra + 32);
+ get_cpu_vsrh(mask, a->vrb + 32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrh(a->vrt + 32, tgt);
+
+ tcg_temp_free_i64(tgt);
+ tcg_temp_free_i64(src);
+ tcg_temp_free_i64(mask);
+
+ return true;
+}