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authorPeter Maydell <peter.maydell@linaro.org>2021-04-12 12:12:09 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-04-12 12:12:09 +0100
commitc1e90def01bdb8fcbdbebd9d1eaa8e4827ece620 (patch)
tree7f497416d1cbfadc9cc2ab5961e8b790eb7eb6b9
parentf2afdc2ad94b99cc98371791cabc308b547e4add (diff)
parent52c01ada86611136e3122dd139788dbcbc292d86 (diff)
downloadqemu-arm-c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620.tar.gz
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging
target-arm queue: * hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts * hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs * accel/tcg: Preserve PAGE_ANON when changing page permissions * target/arm: Check PAGE_WRITE_ORG for MTE writeability * exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 # gpg: Signature made Mon 12 Apr 2021 11:31:15 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210412: exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 target/arm: Check PAGE_WRITE_ORG for MTE writeability accel/tcg: Preserve PAGE_ANON when changing page permissions hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--accel/tcg/translate-all.c9
-rw-r--r--hw/arm/smmuv3.c12
-rw-r--r--hw/arm/virt-acpi-build.c4
-rw-r--r--include/exec/cpu-all.h4
-rw-r--r--target/arm/mte_helper.c2
-rw-r--r--tests/tcg/aarch64/Makefile.target2
-rw-r--r--tests/tcg/aarch64/mte-6.c43
-rw-r--r--tests/tcg/aarch64/mte.h3
8 files changed, 66 insertions, 13 deletions
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index f32df8b240..ba6ab09790 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -2714,6 +2714,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
a missing call to h2g_valid. */
assert(end - 1 <= GUEST_ADDR_MAX);
assert(start < end);
+ /* Only set PAGE_ANON with new mappings. */
+ assert(!(flags & PAGE_ANON) || (flags & PAGE_RESET));
assert_memory_lock();
start = start & TARGET_PAGE_MASK;
@@ -2737,11 +2739,14 @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
p->first_tb) {
tb_invalidate_phys_page(addr, 0);
}
- if (reset_target_data && p->target_data) {
+ if (reset_target_data) {
g_free(p->target_data);
p->target_data = NULL;
+ p->flags = flags;
+ } else {
+ /* Using mprotect on a page does not change MAP_ANON. */
+ p->flags = (p->flags & PAGE_ANON) | flags;
}
- p->flags = flags;
}
}
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 3b87324ce2..8705612535 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -980,16 +980,20 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
}
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
{
- uint32_t start = CMD_SID(&cmd);
+ uint32_t sid = CMD_SID(&cmd), mask;
uint8_t range = CMD_STE_RANGE(&cmd);
- uint64_t end = start + (1ULL << (range + 1)) - 1;
- SMMUSIDRange sid_range = {start, end};
+ SMMUSIDRange sid_range;
if (CMD_SSEC(&cmd)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
- trace_smmuv3_cmdq_cfgi_ste_range(start, end);
+
+ mask = (1ULL << (range + 1)) - 1;
+ sid_range.start = sid & ~mask;
+ sid_range.end = sid_range.start + mask;
+
+ trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
&sid_range);
break;
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f5a2b2d4cb..60fe2e65a7 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -292,8 +292,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
smmu->event_gsiv = cpu_to_le32(irq);
smmu->pri_gsiv = cpu_to_le32(irq + 1);
- smmu->gerr_gsiv = cpu_to_le32(irq + 2);
- smmu->sync_gsiv = cpu_to_le32(irq + 3);
+ smmu->sync_gsiv = cpu_to_le32(irq + 2);
+ smmu->gerr_gsiv = cpu_to_le32(irq + 3);
/* Identity RID mapping covering the whole input RID range */
idmap = &smmu->id_mapping_array[0];
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d76b0b9e02..32cfb634c6 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -268,8 +268,8 @@ extern intptr_t qemu_host_page_mask;
#define PAGE_RESERVED 0x0100
#endif
/* Target-specific bits that will be used via page_get_flags(). */
-#define PAGE_TARGET_1 0x0080
-#define PAGE_TARGET_2 0x0200
+#define PAGE_TARGET_1 0x0200
+#define PAGE_TARGET_2 0x0400
#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 0bbb9ec346..8be17e1b70 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -83,7 +83,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
uint8_t *tags;
uintptr_t index;
- if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) {
+ if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {
/* SIGSEGV */
arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
ptr_mmu_idx, false, ra);
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 56e48f4b34..05b2622bfc 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -37,7 +37,7 @@ AARCH64_TESTS += bti-2
# MTE Tests
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),)
-AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4
+AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-6
mte-%: CFLAGS += -march=armv8.5-a+memtag
endif
diff --git a/tests/tcg/aarch64/mte-6.c b/tests/tcg/aarch64/mte-6.c
new file mode 100644
index 0000000000..60d51d18be
--- /dev/null
+++ b/tests/tcg/aarch64/mte-6.c
@@ -0,0 +1,43 @@
+#include "mte.h"
+
+void pass(int sig, siginfo_t *info, void *uc)
+{
+ assert(info->si_code == SEGV_MTESERR);
+ exit(0);
+}
+
+int main(void)
+{
+ enable_mte(PR_MTE_TCF_SYNC);
+
+ void *brk = sbrk(16);
+ if (brk == (void *)-1) {
+ perror("sbrk");
+ return 2;
+ }
+
+ if (mprotect(brk, 16, PROT_READ | PROT_WRITE | PROT_MTE)) {
+ perror("mprotect");
+ return 2;
+ }
+
+ int *p1, *p2;
+ long excl = 1;
+
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(brk), "r"(excl));
+ asm("gmi %0,%1,%0" : "+r"(excl) : "r"(p1));
+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(brk), "r"(excl));
+ asm("stg %0,[%0]" : : "r"(p1));
+
+ *p1 = 0;
+
+ struct sigaction sa;
+ memset(&sa, 0, sizeof(sa));
+ sa.sa_sigaction = pass;
+ sa.sa_flags = SA_SIGINFO;
+ sigaction(SIGSEGV, &sa, NULL);
+
+ *p2 = 0;
+
+ abort();
+}
diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h
index 141cef522c..0805676b11 100644
--- a/tests/tcg/aarch64/mte.h
+++ b/tests/tcg/aarch64/mte.h
@@ -48,7 +48,8 @@ static void enable_mte(int tcf)
}
}
-static void *alloc_mte_mem(size_t size)
+static void * alloc_mte_mem(size_t size) __attribute__((unused));
+static void * alloc_mte_mem(size_t size)
{
void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE,
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);