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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-01-29 21:23:17 +0800
committerPeter Maydell <peter.maydell@linaro.org>2021-02-02 17:00:55 +0000
commit93722b6f6a6ef0ab0544f20440a2f6b951103dcb (patch)
tree96edd9a76b5cb0b434029ed9c1479a6ea6ca2338
parent9c431a43a62255402a6bbe9a01b0464e73b30fe4 (diff)
downloadqemu-arm-93722b6f6a6ef0ab0544f20440a2f6b951103dcb.tar.gz
hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com [bmeng: add a 'common_reset' function that does most of reset operation] Signed-off-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/ssi/imx_spi.c32
1 files changed, 24 insertions, 8 deletions
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 8fb3c9b6d1..e85be6ae60 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -228,15 +228,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
}
-static void imx_spi_reset(DeviceState *dev)
+static void imx_spi_common_reset(IMXSPIState *s)
{
- IMXSPIState *s = IMX_SPI(dev);
-
- DPRINTF("\n");
-
- memset(s->regs, 0, sizeof(s->regs));
+ int i;
- s->regs[ECSPI_STATREG] = 0x00000003;
+ for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
+ switch (i) {
+ case ECSPI_CONREG:
+ /* CONREG is not updated on soft reset */
+ break;
+ case ECSPI_STATREG:
+ s->regs[i] = 0x00000003;
+ break;
+ default:
+ s->regs[i] = 0;
+ break;
+ }
+ }
imx_spi_rxfifo_reset(s);
imx_spi_txfifo_reset(s);
@@ -246,11 +254,19 @@ static void imx_spi_reset(DeviceState *dev)
static void imx_spi_soft_reset(IMXSPIState *s)
{
- imx_spi_reset(DEVICE(s));
+ imx_spi_common_reset(s);
imx_spi_update_irq(s);
}
+static void imx_spi_reset(DeviceState *dev)
+{
+ IMXSPIState *s = IMX_SPI(dev);
+
+ imx_spi_common_reset(s);
+ s->regs[ECSPI_CONREG] = 0;
+}
+
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t value = 0;