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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-01-29 21:23:18 +0800
committerPeter Maydell <peter.maydell@linaro.org>2021-02-02 17:00:55 +0000
commit7c87bb5333f0fdb17fee7e52acff1d915a68857e (patch)
treeb3a5fe6e68087d37b12d626f6c6e129accc33d0a
parent93722b6f6a6ef0ab0544f20440a2f6b951103dcb (diff)
downloadqemu-arm-7c87bb5333f0fdb17fee7e52acff1d915a68857e.tar.gz
hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-id: 20210129132323.30946-6-bmeng.cn@gmail.com Message-Id: <20210115153049.3353008-5-f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/ssi/imx_spi.c60
1 files changed, 29 insertions, 31 deletions
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index e85be6ae60..21e2c9dea3 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -279,42 +279,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
return 0;
}
- switch (index) {
- case ECSPI_RXDATA:
- if (!imx_spi_is_enabled(s)) {
- value = 0;
- } else if (fifo32_is_empty(&s->rx_fifo)) {
- /* value is undefined */
- value = 0xdeadbeef;
- } else {
- /* read from the RX FIFO */
- value = fifo32_pop(&s->rx_fifo);
- }
-
- break;
- case ECSPI_TXDATA:
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
- TYPE_IMX_SPI, __func__);
-
- /* Reading from TXDATA gives 0 */
-
- break;
- case ECSPI_MSGDATA:
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
- TYPE_IMX_SPI, __func__);
+ value = s->regs[index];
+
+ if (imx_spi_is_enabled(s)) {
+ switch (index) {
+ case ECSPI_RXDATA:
+ if (fifo32_is_empty(&s->rx_fifo)) {
+ /* value is undefined */
+ value = 0xdeadbeef;
+ } else {
+ /* read from the RX FIFO */
+ value = fifo32_pop(&s->rx_fifo);
+ }
+ break;
+ case ECSPI_TXDATA:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "[%s]%s: Trying to read from TX FIFO\n",
+ TYPE_IMX_SPI, __func__);
- /* Reading from MSGDATA gives 0 */
+ /* Reading from TXDATA gives 0 */
+ break;
+ case ECSPI_MSGDATA:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "[%s]%s: Trying to read from MSG FIFO\n",
+ TYPE_IMX_SPI, __func__);
+ /* Reading from MSGDATA gives 0 */
+ break;
+ default:
+ break;
+ }
- break;
- default:
- value = s->regs[index];
- break;
+ imx_spi_update_irq(s);
}
-
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
- imx_spi_update_irq(s);
-
return (uint64_t)value;
}