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authorPeter Maydell <peter.maydell@linaro.org>2020-10-19 16:13:01 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-10-20 16:12:01 +0100
commit8128c8e8cc9489a8387c74075974f86dc0222e7f (patch)
tree573940f3a8b5ad0e08ea71d2f210f776b7620909
parentd31e2ce68d56f5bcc83831497e5fe4b8a7e18e85 (diff)
downloadqemu-arm-8128c8e8cc9489a8387c74075974f86dc0222e7f.tar.gz
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extensionpull-target-arm-20201020-1
If the M-profile low-overhead-branch extension is implemented, FPSCR bits [18:16] are a new field LTPSIZE. If MVE is not implemented (currently always true for us) then this field always reads as 4 and ignores writes. These bits used to be the vector-length field for the old short-vector extension, so we need to take care that they are not misinterpreted as setting vec_len. We do this with a rearrangement of the vfp_set_fpscr() code that deals with vec_len, vec_stride and also the QC bit; this obviates the need for the M-profile only masking step that we used to have at the start of the function. We provide a new field in CPUState for LTPSIZE, even though this will always be 4, in preparation for MVE, so we don't have to come back later and split it out of the vfp.xregs[FPSCR] value. (This state struct field will be saved and restored as part of the FPSCR value via the vmstate_fpscr in machine.c.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201019151301.2046-11-peter.maydell@linaro.org
-rw-r--r--target/arm/cpu.c9
-rw-r--r--target/arm/cpu.h1
-rw-r--r--target/arm/vfp_helper.c6
3 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 186ee621a6..07492e9f9a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -255,6 +255,15 @@ static void arm_cpu_reset(DeviceState *dev)
uint8_t *rom;
uint32_t vecbase;
+ if (cpu_isar_feature(aa32_lob, cpu)) {
+ /*
+ * LTPSIZE is constant 4 if MVE not implemented, and resets
+ * to an UNKNOWN value if MVE is implemented. We choose to
+ * always reset to 4.
+ */
+ env->v7m.ltpsize = 4;
+ }
+
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
env->v7m.secure = true;
} else {
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a432f301f1..49cd5cabcf 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -549,6 +549,7 @@ typedef struct CPUARMState {
uint32_t fpdscr[M_REG_NUM_BANKS];
uint32_t cpacr[M_REG_NUM_BANKS];
uint32_t nsacr;
+ int ltpsize;
} v7m;
/* Information associated with an exception about to be taken:
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 364856498c..01b9d8557f 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -174,6 +174,12 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
| (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
+ /*
+ * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
+ * two is not applicable to this CPU will always be zero.
+ */
+ fpscr |= env->v7m.ltpsize << 16;
+
fpscr |= vfp_get_fpscr_from_host(env);
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];