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authorPeter Maydell <peter.maydell@linaro.org>2020-10-01 17:01:16 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-10-08 21:40:01 +0100
commitd1b6b7017572e8d82f26eb827a1dba0e8cf3cae6 (patch)
treed1138af4168d4cc52fd710ba6c9142391dd6db44
parent68970d1e0d07e3a266141bbd9038fd9890ca88f2 (diff)
downloadqemu-arm-d1b6b7017572e8d82f26eb827a1dba0e8cf3cae6.tar.gz
target/arm: Make '-cpu max' have a 48-bit PApull-target-arm-20201008-1
QEMU supports a 48-bit physical address range, but we don't currently expose it in the '-cpu max' ID registers (you get the same range as Cortex-A57, which is 44 bits). Set the ID_AA64MMFR0.PARange field to indicate 48 bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
-rw-r--r--target/arm/cpu64.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index e00271b932..649213082f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -653,6 +653,10 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
cpu->isar.id_aa64pfr1 = t;
+ t = cpu->isar.id_aa64mmfr0;
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
+ cpu->isar.id_aa64mmfr0 = t;
+
t = cpu->isar.id_aa64mmfr1;
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);