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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-09-01 16:40:58 +0200
committerPeter Maydell <peter.maydell@linaro.org>2020-09-14 14:23:19 +0100
commit7b56d1f4aebf25d81d7b73fe1e2aac2d66b8c0ce (patch)
tree25509af00620a1ffe308d9c4b06c9520993aab81
parent14a560359d24d0f30ced8a2613b83323e9302490 (diff)
downloadqemu-arm-7b56d1f4aebf25d81d7b73fe1e2aac2d66b8c0ce.tar.gz
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
Per the datasheet (DDI0407 r2p0): "All SCU registers are byte accessible" and are 32-bit aligned. Set MemoryRegionOps::valid min/max fields and simplify the write() handler. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200901144100.116742-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/misc/a9scu.c21
1 files changed, 5 insertions, 16 deletions
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index 915f127761..3f3dcc414f 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -52,23 +52,8 @@ static void a9_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
A9SCUState *s = (A9SCUState *)opaque;
- uint32_t mask;
+ uint32_t mask = MAKE_64BIT_MASK(0, size * 8);
uint32_t shift;
- switch (size) {
- case 1:
- mask = 0xff;
- break;
- case 2:
- mask = 0xffff;
- break;
- case 4:
- mask = 0xffffffff;
- break;
- default:
- fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
- size, (unsigned)offset);
- return;
- }
switch (offset) {
case 0x00: /* Control */
@@ -99,6 +84,10 @@ static void a9_scu_write(void *opaque, hwaddr offset,
static const MemoryRegionOps a9_scu_ops = {
.read = a9_scu_read,
.write = a9_scu_write,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
.endianness = DEVICE_NATIVE_ENDIAN,
};