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authorEric Auger <eric.auger@redhat.com>2020-07-28 17:08:12 +0200
committerPeter Maydell <peter.maydell@linaro.org>2020-08-24 10:02:06 +0100
commitf0ec277cd46c0c7b078cc6bc90201999bb0dcd0b (patch)
tree67f3a54b4bc8b0d40ae4acf85c071c11049eadb4
parentd52915616c059ed273caa2d496b58e5d215c5962 (diff)
downloadqemu-arm-f0ec277cd46c0c7b078cc6bc90201999bb0dcd0b.tar.gz
hw/arm/smmuv3: Fix IIDR offset
The SMMU IIDR register is at 0x018 offset. Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton") Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-9-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/arm/smmuv3-internal.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 5babf72f7d..ef093eaff5 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -63,7 +63,7 @@ REG32(IDR5, 0x14)
#define SMMU_IDR5_OAS 4
-REG32(IIDR, 0x1c)
+REG32(IIDR, 0x18)
REG32(CR0, 0x20)
FIELD(CR0, SMMU_ENABLE, 0, 1)
FIELD(CR0, EVENTQEN, 2, 1)