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authorAlistair Francis <alistair.francis@wdc.com>2020-07-24 22:34:40 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-08-21 22:37:55 -0700
commitc43388bbfd0999edacc269e7d06eeaaf19b9d320 (patch)
tree965d6f32c789ac0ec4650771123318eaaa1d7502
parentaf3fc195e3c8e98b62eca3e4ee927f1965381dc3 (diff)
downloadqemu-arm-c43388bbfd0999edacc269e7d06eeaaf19b9d320.tar.gz
hw/intc: ibex_plic: Update the pending irqs
After a claim or a priority change we need to update the pending interrupts. This is based on the same patch for the SiFive PLIC: 55765822804f5a58594e "riscv: plic: Add a couple of mising sifive_plic_update calls" Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Cc: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <0693aa700a4c67c49b3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com>
-rw-r--r--hw/intc/ibex_plic.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 41079518c6..578edd2ce0 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
s->pending[pending_num] &= ~(1 << (s->claim % 32));
ret = s->claim;
+
+ /* Update the interrupt status after the claim */
+ ibex_plic_update(s);
}
return ret;
@@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
} else if (addr_between(addr, s->priority_base, s->priority_num)) {
uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
s->priority[irq] = value & 7;
+ ibex_plic_update(s);
} else if (addr_between(addr, s->enable_base, s->enable_num)) {
uint32_t enable_reg = (addr - s->enable_base) / 4;