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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-07-09 17:23:37 +0200
committerPeter Maydell <peter.maydell@linaro.org>2020-08-24 10:01:40 +0100
commit8cbd4616226aaf0f64599c64162062f0ecc0fe9b (patch)
tree502457ec1d2b1dd622670ef41db573eb11ddeca4
parent8367a77c4d3f6e1e60890f5510304feb2c621611 (diff)
downloadqemu-arm-8cbd4616226aaf0f64599c64162062f0ecc0fe9b.tar.gz
hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
The 'Cortex-A9MPCore internal peripheral' block can only be used with Cortex A5 and A9 cores. As we don't model the A5 yet, simply check the machine cpu core is a Cortex A9. If not return an error. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200709152337.15533-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/cpu/a9mpcore.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 351295e518..ec186d49ab 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
+#include "cpu.h"
#define A9_GIC_NUM_PRIORITY_BITS 5
@@ -52,8 +53,18 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
*wdtbusdev;
int i;
bool has_el3;
+ CPUState *cpu0;
Object *cpuobj;
+ cpu0 = qemu_get_cpu(0);
+ cpuobj = OBJECT(cpu0);
+ if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
+ /* We might allow Cortex-A5 once we model it */
+ error_setg(errp,
+ "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU");
+ return;
+ }
+
scudev = DEVICE(&s->scu);
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -70,7 +81,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
*/
- cpuobj = OBJECT(qemu_get_cpu(0));
has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);