diff options
authorPeter Maydell <peter.maydell@linaro.org>2020-08-03 14:28:15 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-08-24 10:15:11 +0100
commit8b4c9a50dc9531a729ae4b5941d287ad0422db48 (patch)
parente60527c5d501e5015a119a0388a27abeae4dac09 (diff)
target/arm/translate.c: Delete/amend incorrect comments
In arm_tr_init_disas_context() we have a FIXME comment that suggests "cpu_M0 can probably be the same as cpu_V0". This isn't in fact possible: cpu_V0 is used as a temporary inside gen_iwmmxt_shift(), and that function is called in various places where cpu_M0 contains a live value (i.e. between gen_op_iwmmxt_movq_M0_wRn() and gen_op_iwmmxt_movq_wRn_M0() calls). Remove the comment. We also have a comment on the declarations of cpu_V0/V1/M0 which claims they're "for efficiency". This isn't true with modern TCG, so replace this comment with one which notes that they're only used with the iwmmxt decode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200803132815.3861-1-peter.maydell@linaro.org
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4ffd8b1fbe..dd25adcf40 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -57,8 +57,9 @@
#define IS_USER(s) (s->user)
-/* We reuse the same 64-bit temporaries for efficiency. */
+/* These are TCG temporaries used only by the legacy iwMMXt decoder */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
+/* These are TCG globals which alias CPUARMState fields */
static TCGv_i32 cpu_R[16];
TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
TCGv_i64 cpu_exclusive_addr;
@@ -8566,7 +8567,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
cpu_V0 = tcg_temp_new_i64();
cpu_V1 = tcg_temp_new_i64();
- /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
cpu_M0 = tcg_temp_new_i64();