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authorRichard Henderson <richard.henderson@linaro.org>2019-10-23 11:00:45 -0400
committerPeter Maydell <peter.maydell@linaro.org>2019-10-24 17:16:28 +0100
commit3d74e2e9ffc9fda4da2c29ec8975e2115aaaa603 (patch)
treeca31005651275bacad310fb5ded983da32e21c34
parent0a54d68e212a17ae347f40488acef69e63b7bbb4 (diff)
downloadqemu-arm-3d74e2e9ffc9fda4da2c29ec8975e2115aaaa603.tar.gz
target/arm: Add arm_rebuild_hflags
This function assumes nothing about the current state of the cpu, and writes the computed value to env->hflags. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/cpu.h6
-rw-r--r--target/arm/helper.c30
2 files changed, 28 insertions, 8 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9909ff89d4..d844ea21d8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3298,6 +3298,12 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
*opaque);
/**
+ * arm_rebuild_hflags:
+ * Rebuild the cached TBFLAGS for arbitrary changed processor state.
+ */
+void arm_rebuild_hflags(CPUARMState *env);
+
+/**
* aa32_vfp_dreg:
* Return a pointer to the Dn register within env in 32-bit mode.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 89aa6fd933..85de96d071 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11198,17 +11198,35 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
+static uint32_t rebuild_hflags_internal(CPUARMState *env)
+{
+ int el = arm_current_el(env);
+ int fp_el = fp_exception_el(env, el);
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
+
+ if (is_a64(env)) {
+ return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
+ } else if (arm_feature(env, ARM_FEATURE_M)) {
+ return rebuild_hflags_m32(env, fp_el, mmu_idx);
+ } else {
+ return rebuild_hflags_a32(env, fp_el, mmu_idx);
+ }
+}
+
+void arm_rebuild_hflags(CPUARMState *env)
+{
+ env->hflags = rebuild_hflags_internal(env);
+}
+
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
- ARMMMUIdx mmu_idx = arm_mmu_idx(env);
- int current_el = arm_current_el(env);
- int fp_el = fp_exception_el(env, current_el);
uint32_t flags, pstate_for_ss;
+ flags = rebuild_hflags_internal(env);
+
if (is_a64(env)) {
*pc = env->pc;
- flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx);
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
}
@@ -11217,8 +11235,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
*pc = env->regs[15];
if (arm_feature(env, ARM_FEATURE_M)) {
- flags = rebuild_hflags_m32(env, fp_el, mmu_idx);
-
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
!= env->v7m.secure) {
@@ -11242,8 +11258,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
}
} else {
- flags = rebuild_hflags_a32(env, fp_el, mmu_idx);
-
/*
* Note that XSCALE_CPAR shares bits with VECSTRIDE.
* Note that VECLEN+VECSTRIDE are RES0 for M-profile.