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authorPeter Maydell <peter.maydell@linaro.org>2019-02-21 18:17:47 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-21 18:17:47 +0000
commit74ecf7677b72084b25ace9de3191abe3afdaeff6 (patch)
tree236d36fa6f232a3060d39430018cd7570950704d
parent76b09fafaf54051ccc0620169ae5b72c87f4f547 (diff)
downloadqemu-arm-74ecf7677b72084b25ace9de3191abe3afdaeff6.tar.gz
hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header comment
In commit 4b635cf7a95e501211 we added a QOM property to the ARMSSE object, but forgot to add it to the documentation comment in the header. Correct the omission. Fixes: 4b635cf7a95e501211 ("hw/arm/armsse: Make SRAM bank size configurable") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--include/hw/arm/armsse.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index f800bafb14..444605b44d 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -46,6 +46,8 @@
* being the same for both, to avoid having to have separate Property
* lists for different variants. This restriction can be relaxed later
* if necessary.)
+ * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
+ * address of each SRAM bank (and thus the total amount of internal SRAM)
* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
* which are wired to its NVIC lines 32 .. n+32
* + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for