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authorRichard Henderson <richard.henderson@linaro.org>2019-02-21 18:17:45 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-21 18:17:45 +0000
commit3c3ff68492c2d00bd8cb39ed2d02bdaf5caf5cb8 (patch)
tree030b6c362491c70141c993ad9fd93fe3c386555f
parent67da43d668320e1bcb0a0195aaf2de4ff2a001a0 (diff)
downloadqemu-arm-3c3ff68492c2d00bd8cb39ed2d02bdaf5caf5cb8.tar.gz
target/arm: Restructure disas_fp_int_conv
For opcodes 0-5, move some if conditions into the structure of a switch statement. For opcodes 6 & 7, decode everything at once with a second switch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/translate-a64.c90
1 files changed, 47 insertions, 43 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index af8e4fd4be..dbce24fe32 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6541,68 +6541,72 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
int type = extract32(insn, 22, 2);
bool sbit = extract32(insn, 29, 1);
bool sf = extract32(insn, 31, 1);
+ bool itof = false;
if (sbit) {
- unallocated_encoding(s);
- return;
+ goto do_unallocated;
}
- if (opcode > 5) {
- /* FMOV */
- bool itof = opcode & 1;
-
- if (rmode >= 2) {
- unallocated_encoding(s);
- return;
+ switch (opcode) {
+ case 2: /* SCVTF */
+ case 3: /* UCVTF */
+ itof = true;
+ /* fallthru */
+ case 4: /* FCVTAS */
+ case 5: /* FCVTAU */
+ if (rmode != 0) {
+ goto do_unallocated;
}
-
- switch (sf << 3 | type << 1 | rmode) {
- case 0x0: /* 32 bit */
- case 0xa: /* 64 bit */
- case 0xd: /* 64 bit to top half of quad */
+ /* fallthru */
+ case 0: /* FCVT[NPMZ]S */
+ case 1: /* FCVT[NPMZ]U */
+ switch (type) {
+ case 0: /* float32 */
+ case 1: /* float64 */
break;
- case 0x6: /* 16-bit float, 32-bit int */
- case 0xe: /* 16-bit float, 64-bit int */
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
+ case 3: /* float16 */
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ goto do_unallocated;
}
- /* fallthru */
+ break;
default:
- /* all other sf/type/rmode combinations are invalid */
- unallocated_encoding(s);
- return;
+ goto do_unallocated;
}
-
if (!fp_access_check(s)) {
return;
}
- handle_fmov(s, rd, rn, type, itof);
- } else {
- /* actual FP conversions */
- bool itof = extract32(opcode, 1, 1);
+ handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
+ break;
- if (rmode != 0 && opcode > 1) {
- unallocated_encoding(s);
- return;
- }
- switch (type) {
- case 0: /* float32 */
- case 1: /* float64 */
- break;
- case 3: /* float16 */
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
+ default:
+ switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
+ case 0b01100110: /* FMOV half <-> 32-bit int */
+ case 0b01100111:
+ case 0b11100110: /* FMOV half <-> 64-bit int */
+ case 0b11100111:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ goto do_unallocated;
}
/* fallthru */
+ case 0b00000110: /* FMOV 32-bit */
+ case 0b00000111:
+ case 0b10100110: /* FMOV 64-bit */
+ case 0b10100111:
+ case 0b11001110: /* FMOV top half of 128-bit */
+ case 0b11001111:
+ if (!fp_access_check(s)) {
+ return;
+ }
+ itof = opcode & 1;
+ handle_fmov(s, rd, rn, type, itof);
+ break;
+
default:
+ do_unallocated:
unallocated_encoding(s);
return;
}
-
- if (!fp_access_check(s)) {
- return;
- }
- handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
+ break;
}
}