diff options
| author | Alex Bennée <alex.bennee@linaro.org> | 2019-02-15 09:56:38 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-15 09:56:38 +0000 |
| commit | b5bd7440422bb66deaceb812bb9287a6a3cdf10c (patch) | |
| tree | 91210051e97d3019452d27365229de29dd73195a | |
| parent | abd5abc58c5d4c9bd23427b0998a44eb87ed47a2 (diff) | |
target/arm: relax permission checks for HWCAP_CPUID registers
Although technically not visible to userspace the kernel does make
them visible via a trap and emulate ABI. We provide a new permission
mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust
the minimum permission check accordingly.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20190205190224.2198-2-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu.h | 12 | ||||
| -rw-r--r-- | target/arm/helper.c | 6 |
2 files changed, 17 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47238e4245..c92c097b44 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2226,6 +2226,18 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index e1ef2f3523..88cf497603 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6857,7 +6857,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != ARM_CP_STATE_AA32) { int mask = 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: + /* min_EL EL1, but some accessible to EL0 via kernel ABI */ + mask = PL0U_R | PL1_RW; + break; + case 1: case 2: /* min_EL EL1 */ mask = PL1_RW; break; |