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authorAaron Lindsay <aaron@os.amperecomputing.com>2018-12-11 15:20:49 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-01-18 14:10:08 +0000
commit3c1e0f4cb2d6d38253a63d88055359eb11c435d3 (patch)
tree8e65e10f550cdd2962a51ec841d7effe59e5515d
parent2d4924c81f490e1d8f40208447b9d375da197bfd (diff)
downloadqemu-arm-3c1e0f4cb2d6d38253a63d88055359eb11c435d3.tar.gz
target/arm: PMU: Set PMCR.N to 4
This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-13-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/helper.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 35c105a861..44f1340ee1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1777,7 +1777,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_W, .type = ARM_CP_NOP },
/* Performance monitors are implementation defined in v7,
* but with an ARM recommended set of registers, which we
- * follow (although we don't actually implement any counters)
+ * follow.
*
* Performance registers fall into three categories:
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
@@ -5671,10 +5671,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
- * field as main ID register, and we implement only the cycle
- * count register.
+ * field as main ID register, and we implement four counters in
+ * addition to the cycle count register.
*/
- unsigned int i, pmcrn = 0;
+ unsigned int i, pmcrn = 4;
ARMCPRegInfo pmcr = {
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
.access = PL0_RW,
@@ -5689,7 +5689,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = cpu->midr & 0xff000000,
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
.writefn = pmcr_write, .raw_writefn = raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);