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authorAaron Lindsay <aclindsa@gmail.com>2018-10-10 16:37:23 -0400
committerPeter Maydell <peter.maydell@linaro.org>2018-10-16 17:14:55 +0100
commit599b71e277ac7e92807191b20b7163a28c5450ad (patch)
tree629070c14884077d7175290a458da5ab81cebbfc
parentfc5f6856a02168864a5c1a46866a12839322222f (diff)
downloadqemu-arm-599b71e277ac7e92807191b20b7163a28c5450ad.tar.gz
target/arm: Mask PMOVSR writes based on supported counters
This is an amendment to my earlier patch: commit 7ece99b17e832065236c07a158dfac62619ef99b Author: Aaron Lindsay <alindsay@codeaurora.org> Date: Thu Apr 26 11:04:39 2018 +0100 target/arm: Mask PMU register writes based on PMCR_EL0.N Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181010203735.27918-3-aclindsa@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/helper.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 138a1f1540..7a53098888 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1179,6 +1179,7 @@ static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ value &= pmu_counter_mask(env);
env->cp15.c9_pmovsr &= ~value;
}