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authorPeter Maydell <peter.maydell@linaro.org>2018-08-14 17:17:21 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-14 17:17:21 +0100
commit3d0e3080d8b7abcddc038d18e8401861c369c4c1 (patch)
tree27b2dd726573b1e0ca10668c25b939e2753a662d
parentac656b166b57332ee397e9781810c956f4f5fde5 (diff)
target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set
One of the required effects of setting HCR_EL2.TGE is that when SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for all purposes except direct reads. That is, it effectively disables the MMU for the NS EL0/EL1 translation regime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-6-peter.maydell@linaro.org
-rw-r--r--target/arm/helper.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7b438e43a9..62f63e4e5b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8396,6 +8396,14 @@ static inline bool regime_translation_disabled(CPUARMState *env,
if (mmu_idx == ARMMMUIdx_S2NS) {
return (env->cp15.hcr_el2 & HCR_VM) == 0;
}
+
+ if (env->cp15.hcr_el2 & HCR_TGE) {
+ /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
+ if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
+ return true;
+ }
+ }
+
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
}