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authorPeter Maydell <peter.maydell@linaro.org>2017-07-11 11:21:26 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-07-11 11:21:26 +0100
commit792dac309c8660306557ba058b8b5a6a75ab3c1f (patch)
treec6448caf17db30d783454f82dfe09a99ba07baed
parent5d721b785fbe80170fc756e9444cf751d3a47568 (diff)
downloadqemu-arm-pull-target-arm-20170711.tar.gz
target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread modepull-target-arm-20170711
For v7M, writes to the CONTROL register are only permitted for privileged code. However even if the code is privileged, the write must not affect the SPSEL bit in the CONTROL register if the CPU is in Thread mode (as documented in the pseudocode for the MSR instruction). Implement this, instead of permitting SPSEL to be written in all cases. This was causing mbed applications not to run, because the RTX RTOS they use relies on this behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1498820791-8130-1-git-send-email-peter.maydell@linaro.org
-rw-r--r--target/arm/helper.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2594faa9b8..4ed32c56b8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8768,9 +8768,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
}
break;
case 20: /* CONTROL */
- switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
- env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK |
- R_V7M_CONTROL_NPRIV_MASK);
+ /* Writing to the SPSEL bit only has an effect if we are in
+ * thread mode; other bits can be updated by any privileged code.
+ * switch_v7m_sp() deals with updating the SPSEL bit in
+ * env->v7m.control, so we only need update the others.
+ */
+ if (env->v7m.exception == 0) {
+ switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
+ }
+ env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;
+ env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"