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authorPeter Maydell <peter.maydell@linaro.org>2017-02-07 18:29:59 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-07 18:29:59 +0000
commit63f26fcfda8e19f94ce23336726d14805250a5b6 (patch)
treedb05bcf89f22fa48f039e39764f531376fe62a9f
parent40612000599e52e792d23c998377a0fa429c4036 (diff)
target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
In the ARM ldr/str decode path, rather than directly testing "insn & (1 << 21)" and "insn & (1 << 24)", abstract these bits out into wbit and pbit local flags. (We will want to do more tests against them to determine whether we need to provide syndrome information.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--target/arm/translate.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 493c627bcf..175b4c1cb7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8782,6 +8782,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
} else {
int address_offset;
bool load = insn & (1 << 20);
+ bool wbit = insn & (1 << 21);
+ bool pbit = insn & (1 << 24);
bool doubleword = false;
/* Misc load/store */
rn = (insn >> 16) & 0xf;
@@ -8799,8 +8801,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
addr = load_reg(s, rn);
- if (insn & (1 << 24))
+ if (pbit) {
gen_add_datah_offset(s, insn, 0, addr);
+ }
address_offset = 0;
if (doubleword) {
@@ -8849,10 +8852,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
ensure correct behavior with overlapping index registers.
ldrd with base writeback is undefined if the
destination and index registers overlap. */
- if (!(insn & (1 << 24))) {
+ if (!pbit) {
gen_add_datah_offset(s, insn, address_offset, addr);
store_reg(s, rn, addr);
- } else if (insn & (1 << 21)) {
+ } else if (wbit) {
if (address_offset)
tcg_gen_addi_i32(addr, addr, address_offset);
store_reg(s, rn, addr);