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authorPeter Maydell <peter.maydell@linaro.org>2016-04-04 17:33:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-04-04 17:33:52 +0100
commitbf06c1123a427fefc2cf9cf8019578eafc19eb6f (patch)
tree0bb315c6c4c906b40a2fc92b19a7bb760c39aa97
parent094a7d0b9d10812d06be2c5c19288cee4603c693 (diff)
downloadqemu-arm-pull-target-arm-20160404.tar.gz
target-arm: Make the 64-bit version of VTCR do the migrationpull-target-arm-20160404
Move the ALIAS tag from VTCR_EL2 to VTCR so that we migrate the 64-bit version, as is usual. (This has no particular effect now unless the guest wrote to the high RES0 bits of VTCR_EL2.) Add a comment about why it's OK that we don't have the various accessor functions that the EL1 TCR regdefs do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1459435778-5526-4-git-send-email-peter.maydell@linaro.org
-rw-r--r--target-arm/helper.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0e54d90e11..09638b2e7d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3564,11 +3564,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
{ .name = "VTCR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
+ .type = ARM_CP_ALIAS,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
.fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
- .access = PL2_RW, .type = ARM_CP_ALIAS,
+ .access = PL2_RW,
+ /* no .writefn needed as this can't cause an ASID change;
+ * no .raw_writefn or .resetfn needed as we never use mask/base_mask
+ */
.fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 6, .crm = 2,