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authorYongbok Kim <yongbok.kim@imgtec.com>2015-06-25 00:24:14 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-06-26 09:09:42 +0100
commite60ec06357470db5a0f25901ca19b6237e6da927 (patch)
tree511aa0bcd7b1c9bc4696b944b4d1d6beee5bed68
parent1bf5902de03732d4067c4e90171a1741d6542c45 (diff)
downloadqemu-arm-e60ec06357470db5a0f25901ca19b6237e6da927.tar.gz
target-mips: add microMIPS TLBINV, TLBINVF
Add microMIPS TLBINV, TLBINVF Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
-rw-r--r--target-mips/translate.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 02c2523207..abff2ab564 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12243,6 +12243,8 @@ enum {
TLBR = 0x1,
TLBWI = 0x2,
TLBWR = 0x3,
+ TLBINV = 0x4,
+ TLBINVF = 0x5,
WAIT = 0x9,
IRET = 0xd,
DERET = 0xe,
@@ -13027,6 +13029,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
case TLBWR:
mips32_op = OPC_TLBWR;
goto do_cp0;
+ case TLBINV:
+ mips32_op = OPC_TLBINV;
+ goto do_cp0;
+ case TLBINVF:
+ mips32_op = OPC_TLBINVF;
+ goto do_cp0;
case WAIT:
mips32_op = OPC_WAIT;
goto do_cp0;