diff options
| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2014-05-28 08:28:21 +0100 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2014-06-05 21:00:03 +0100 |
| commit | fd7fbc8ff713ebf8fa2ae5078f1024079bde90b1 (patch) | |
| tree | dc5ebbbdbdc6d080ce2983435c5508d9e8200db2 | |
| parent | ea9a6606b1559baaf4ddeba3cdce9858055f4044 (diff) | |
apb: fix IOMMU register sizes
According to the referenced documentation, the IOMMU has 3 64-bit registers
consisting of a control register, base register and flush register.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
| -rw-r--r-- | hw/pci-host/apb.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index bea7092eeb..e25791fcdd 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -71,7 +71,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define NO_IRQ_REQUEST (MAX_IVEC + 1) typedef struct IOMMUState { - uint32_t regs[4]; + uint32_t regs[6]; } IOMMUState; #define TYPE_APB "pbm" @@ -157,11 +157,9 @@ static void apb_config_writel (void *opaque, hwaddr addr, case 0x30 ... 0x4f: /* DMA error registers */ /* XXX: not implemented yet */ break; - case 0x200 ... 0x20b: /* IOMMU */ + case 0x200 ... 0x217: /* IOMMU */ is->regs[(addr & 0xf) >> 2] = val; break; - case 0x20c ... 0x3ff: /* IOMMU flush */ - break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { unsigned int ino = (addr & 0x3f) >> 3; @@ -241,12 +239,9 @@ static uint64_t apb_config_readl (void *opaque, val = 0; /* XXX: not implemented yet */ break; - case 0x200 ... 0x20b: /* IOMMU */ + case 0x200 ... 0x217: /* IOMMU */ val = is->regs[(addr & 0xf) >> 2]; break; - case 0x20c ... 0x3ff: /* IOMMU flush */ - val = 0; - break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { val = s->pci_irq_map[(addr & 0x3f) >> 3]; |