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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:55 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:55 +0100
commita1ba125c0ca64b604484ddc104e533546d92088a (patch)
tree5e1816a48b55a864fd3be7107ee1e5130bb96db8
parentd42e3c26cd21677eacca76386b95093f2f67803f (diff)
downloadqemu-arm-a1ba125c0ca64b604484ddc104e533546d92088a.tar.gz
target-arm: A64: Register VBAR_EL3pull-target-arm-20140527
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-24-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/cpu.h2
-rw-r--r--target-arm/helper.c5
2 files changed, 6 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3ccbd95143..8d04385261 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -198,7 +198,7 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
- uint64_t vbar_el[3]; /* vector base address register */
+ uint64_t vbar_el[4]; /* vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c769ef25a5..6a01c6a82a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2138,6 +2138,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
+ { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
+ .access = PL3_RW, .writefn = vbar_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
+ .resetvalue = 0 },
REGINFO_SENTINEL
};