diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-08-22 17:31:14 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-08-22 17:31:14 +0100 |
| commit | cd1e4db73646006039f25879af3bff55b2295ff3 (patch) | |
| tree | 9a1eab0f9cf5da24f6e1ab42f05a2854f569d99e | |
| parent | 4b3520fd93cd49cc56dfcab45d90735cc2e35af7 (diff) | |
target/arm: Fix 64-bit SSRApull-target-arm-20230824
Typo applied byte-wise shift instead of double-word shift.
Cc: qemu-stable@nongnu.org
Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230821022025.397682-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/tcg/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b71ac2d0d5..39541ecdf0 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3053,7 +3053,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, .vece = MO_32 }, { .fni8 = gen_ssra64_i64, .fniv = gen_ssra_vec, - .fno = gen_helper_gvec_ssra_b, + .fno = gen_helper_gvec_ssra_d, .prefer_i64 = TCG_TARGET_REG_BITS == 64, .opt_opc = vecop_list, .load_dest = true, |