diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-10-01 17:01:16 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 15:24:32 +0100 |
| commit | ba118c26e16a97e6ff6de8184057d3420ce16a23 (patch) | |
| tree | 6ccf0fcdcd57851b5add0aaf7887778e7b945cf9 | |
| parent | 777895c033d1e052f1ae07045aab4bc3aed0704f (diff) | |
target/arm: Make '-cpu max' have a 48-bit PApull-target-arm-20201008
QEMU supports a 48-bit physical address range, but we don't currently
expose it in the '-cpu max' ID registers (you get the same range as
Cortex-A57, which is 44 bits).
Set the ID_AA64MMFR0.PARange field to indicate 48 bits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/cpu64.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e00271b932..649213082f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -653,6 +653,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; + t = cpu->isar.id_aa64mmfr0; + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + cpu->isar.id_aa64mmfr0 = t; + t = cpu->isar.id_aa64mmfr1; t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); |