diff options
| author | Sergey Sorokin <afarallax@yandex.ru> | 2016-09-06 19:52:17 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-09-06 19:52:17 +0100 |
| commit | e0fe723c24562c8f909bb40f131bfdbe75650677 (patch) | |
| tree | 9547736c202f8d4f4f456051d37ce488b1617e5c | |
| parent | c2da8a8b90faf0b77417e08fa942af1ff0f7cdc3 (diff) | |
target-arm: Fix lpae bit in FSR on an alignment fault
If an alignment fault occurred and target EL is using AArch32,
then DFSR/IFSR bit LPAE[9] must be set correctly.
Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
Message-id: 1471283293-169850-1-git-send-email-afarallax@yandex.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/op_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 3e8588ee6a..be27b21d52 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -194,7 +194,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, * the LPAE long descriptor format, or the short descriptor format */ if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { - env->exception.fsr = 0x21; + env->exception.fsr = (1 << 9) | 0x21; } else { env->exception.fsr = 0x1; } |