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authorPeter Maydell <peter.maydell@linaro.org>2020-12-11 23:05:05 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-01-08 16:28:09 +0000
commit11863835de10df6e97dfef40e80862764eb092e0 (patch)
treebec455071dd6aa21b2452bd58deb8a438dfe6215
parentd5b70cc5c370b554494b09355f511b7edfcadf62 (diff)
downloadqemu-arm-11863835de10df6e97dfef40e80862764eb092e0.tar.gz
hw/ppc/ppc405_uc: Drop use of ppcuic_init()
Switch the ppc405_uc boards to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. We retain the API feature of ppc405ep_init() where it passes back something allowing the callers to wire up devices to the UIC if they need to, even though neither of the callsites currently makes use of this ability -- instead of passing back the qemu_irq array we pass back the UIC DeviceState. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/ppc/ppc405.h2
-rw-r--r--hw/ppc/ppc405_boards.c8
-rw-r--r--hw/ppc/ppc405_uc.c70
3 files changed, 47 insertions, 33 deletions
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index e6c702f7e0..c58f739886 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -66,7 +66,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
hwaddr ram_bases[2],
hwaddr ram_sizes[2],
- uint32_t sysclk, qemu_irq **picp,
+ uint32_t sysclk, DeviceState **uicdev,
int do_init);
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index b7249f21cf..8f77887fb1 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -151,7 +151,6 @@ static void ref405ep_init(MachineState *machine)
CPUPPCState *env;
DeviceState *dev;
SysBusDevice *s;
- qemu_irq *pic;
MemoryRegion *bios;
MemoryRegion *sram = g_new(MemoryRegion, 1);
ram_addr_t bdloc;
@@ -167,6 +166,7 @@ static void ref405ep_init(MachineState *machine)
int len;
DriveInfo *dinfo;
MemoryRegion *sysmem = get_system_memory();
+ DeviceState *uicdev;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@@ -184,7 +184,7 @@ static void ref405ep_init(MachineState *machine)
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
- 33333333, &pic, kernel_filename == NULL ? 0 : 1);
+ 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
sram_size = 512 * KiB;
memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
@@ -429,7 +429,6 @@ static void taihu_405ep_init(MachineState *machine)
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
char *filename;
- qemu_irq *pic;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *bios;
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
@@ -440,6 +439,7 @@ static void taihu_405ep_init(MachineState *machine)
int linux_boot;
int fl_idx;
DriveInfo *dinfo;
+ DeviceState *uicdev;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine)
"taihu_405ep.ram-1", machine->ram, ram_bases[1],
ram_sizes[1]);
ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
- 33333333, &pic, kernel_filename == NULL ? 0 : 1);
+ 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
fl_idx = 0;
#if defined(USE_FLASH_BIOS)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3e191ae4af..fe047074a1 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -36,6 +36,9 @@
#include "sysemu/sysemu.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
+#include "hw/intc/ppc-uic.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
//#define DEBUG_OPBA
//#define DEBUG_SDRAM
@@ -1446,14 +1449,15 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
hwaddr ram_bases[2],
hwaddr ram_sizes[2],
- uint32_t sysclk, qemu_irq **picp,
+ uint32_t sysclk, DeviceState **uicdevp,
int do_init)
{
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
PowerPCCPU *cpu;
CPUPPCState *env;
- qemu_irq *pic, *irqs;
+ DeviceState *uicdev;
+ SysBusDevice *uicsbd;
memset(clk_setup, 0, sizeof(clk_setup));
/* init CPUs */
@@ -1474,59 +1478,69 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
/* Initialize timers */
ppc_booke_timers_init(cpu, sysclk, 0);
/* Universal interrupt controller */
- irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
- irqs[PPCUIC_OUTPUT_INT] =
- ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
- irqs[PPCUIC_OUTPUT_CINT] =
- ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
- pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
- *picp = pic;
+ uicdev = qdev_new(TYPE_PPC_UIC);
+ uicsbd = SYS_BUS_DEVICE(uicdev);
+
+ object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
+ &error_fatal);
+ sysbus_realize_and_unref(uicsbd, &error_fatal);
+
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
+ ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
+ ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
+
+ *uicdevp = uicdev;
+
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
- dma_irqs[0] = pic[5];
- dma_irqs[1] = pic[6];
- dma_irqs[2] = pic[7];
- dma_irqs[3] = pic[8];
+ dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
+ dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
+ dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
+ dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
ppc405_dma_init(env, dma_irqs);
/* IIC controller */
- sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
+ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
+ qdev_get_gpio_in(uicdev, 2));
/* GPIO */
ppc405_gpio_init(0xef600700);
/* Serial ports */
if (serial_hd(0) != NULL) {
- serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
+ serial_mm_init(address_space_mem, 0xef600300, 0,
+ qdev_get_gpio_in(uicdev, 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
- serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
+ serial_mm_init(address_space_mem, 0xef600400, 0,
+ qdev_get_gpio_in(uicdev, 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
/* OCM */
ppc405_ocm_init(env);
/* GPT */
- gpt_irqs[0] = pic[19];
- gpt_irqs[1] = pic[20];
- gpt_irqs[2] = pic[21];
- gpt_irqs[3] = pic[22];
- gpt_irqs[4] = pic[23];
+ gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
+ gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
+ gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
+ gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
+ gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
ppc4xx_gpt_init(0xef600000, gpt_irqs);
/* PCI */
- /* Uses pic[3], pic[16], pic[18] */
+ /* Uses UIC IRQs 3, 16, 18 */
/* MAL */
- mal_irqs[0] = pic[11];
- mal_irqs[1] = pic[12];
- mal_irqs[2] = pic[13];
- mal_irqs[3] = pic[14];
+ mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
+ mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
+ mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
+ mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
ppc4xx_mal_init(env, 4, 2, mal_irqs);
/* Ethernet */
- /* Uses pic[9], pic[15], pic[17] */
+ /* Uses UIC IRQs 9, 15, 17 */
/* CPU control */
ppc405ep_cpc_init(env, clk_setup, sysclk);