omap3 boot rom emulation changes

- do not map boot rom at address zero
- make use of the arm cp15 vector base address register
- run boot rom emulation from omap3 instead of board

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>

5 files changed, 57 insertions, 43 deletions

diff --git a/hw/beagle.c b/hw/beagle.c
index ef529a61e7..1dea2bd337 100644
--- a/hw/beagle.c
+++ b/hw/beagle.c
@@ -68,7 +68,7 @@ static void beagle_common_init(ram_addr_t ram_size,
 #if MAX_SERIAL_PORTS < 1
 #error MAX_SERIAL_PORTS must be at least 1!
 #endif
-    s->cpu = omap3_mpu_init(cpu_model, ram_size,
+    s->cpu = omap3_mpu_init(cpu_model, 1, ram_size,
                             NULL, NULL, serial_hds[0], NULL);
 
     s->nand = nand_init(NAND_MFR_MICRON, 0xba, dmtd ? dmtd->bdrv : NULL);
@@ -104,8 +104,6 @@ static void beagle_common_init(ram_addr_t ram_size,
     omap_gpmc_attach(s->cpu->gpmc, BEAGLE_SMC_CS, s->smc, 0, 0);
 
     omap_lcd_panel_attach(s->cpu->dss);
-
-    omap3_boot_rom_emu(s->cpu);
 }
 
 static void beagle_xm_init(ram_addr_t ram_size,
diff --git a/hw/nseries.c b/hw/nseries.c
index 3b889deb4b..e80967f7d5 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -2438,7 +2438,7 @@ static void n900_init(ram_addr_t ram_size,
 #if MAX_SERIAL_PORTS < 3
 #error MAX_SERIAL_PORTS must be at least 3!
 #endif
-    s->cpu = omap3_mpu_init(omap3430, N900_SDRAM_SIZE,
+    s->cpu = omap3_mpu_init(omap3430, 1, N900_SDRAM_SIZE,
                             serial_hds[1], serial_hds[2],
                             serial_hds[0], NULL);
     omap_lcd_panel_attach(s->cpu->dss);
diff --git a/hw/omap.h b/hw/omap.h
index de9216b7c7..8a745aa252 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -1130,7 +1130,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
                 const char *core);
 
 /* omap3.c */
-struct omap_mpu_state_s *omap3_mpu_init(int model,
+struct omap_mpu_state_s *omap3_mpu_init(int model, int emulate_bootrom,
                                         unsigned long sdram_size,
                                         CharDriverState *chr_uart1,
                                         CharDriverState *chr_uart2,
@@ -1138,6 +1138,7 @@ struct omap_mpu_state_s *omap3_mpu_init(int model,
                                         CharDriverState *chr_uart4);
 
 /* omap3_boot.c */
+void omap3_boot_rom_init(struct omap_mpu_state_s *s);
 void omap3_boot_rom_emu(struct omap_mpu_state_s *s);
 
 # if TARGET_PHYS_ADDR_BITS == 32
diff --git a/hw/omap3.c b/hw/omap3.c
index cc75451199..90165efdd4 100644
--- a/hw/omap3.c
+++ b/hw/omap3.c
@@ -4047,6 +4047,8 @@ static void omap3_reset(void *opaque)
     omap_synctimer_reset(s->synctimer);
     omap_sdrc_reset(s->sdrc);
     omap_gpmc_reset(s->gpmc);
+    
+    omap3_boot_rom_emu(s);
 }
 
 static const struct dma_irq_map omap3_dma_irq_map[] = {
@@ -4062,7 +4064,7 @@ static int omap3_validate_addr(struct omap_mpu_state_s *s,
     return 1;
 }
 
-struct omap_mpu_state_s *omap3_mpu_init(int model,
+struct omap_mpu_state_s *omap3_mpu_init(int model, int emulate_bootrom,
                                         unsigned long sdram_size,
                                         CharDriverState *chr_uart1,
                                         CharDriverState *chr_uart2,
@@ -4395,6 +4397,10 @@ struct omap_mpu_state_s *omap3_mpu_init(int model,
     sysbus_mmio_map(busdev, 3,
                     omap_l4_base(omap3_l4ta_init(s->l4, L4A_MCSPI4), 0));
     
+    if (emulate_bootrom) {
+        omap3_boot_rom_init(s);
+    }
+    
     qemu_register_reset(omap3_reset, s);
     return s;
 }
diff --git a/hw/omap3_boot.c b/hw/omap3_boot.c
index ebc9f47158..411b111dff 100644
--- a/hw/omap3_boot.c
+++ b/hw/omap3_boot.c
@@ -144,27 +144,29 @@ static const uint8_t omap3_boot_rom[] = { /* 0x40014000-0x4001bfff */
      * boot loader after it has been read into memory */
     0xc8, 0x10, 0x1f, 0xe5, /* ldr r1, [#0x40014040] @ boot loader start */
     0xb0, 0x0c, 0x0f, 0xe3, /* movw r0, #0xfcb0 */
-    0x20, 0x00, 0x44, 0xe3, /* movt r0, #0x4020   @ stack top at 0x4020fcb0 */
-    0xdf, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdf  @ enter SYS mode */
+    0x20, 0x00, 0x44, 0xe3, /* movt r0, #0x4020    @ stack top at 0x4020fcb0 */
+    0xdf, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdf   @ enter SYS mode */
     0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
-    0x80, 0x0c, 0x40, 0xe2, /* sub r0, r0, #32768 @ 32kB SYS/USR stack */
-    0xd1, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd1  @ enter FIQ mode */
+    0x80, 0x0c, 0x40, 0xe2, /* sub r0, r0, #32768  @ 32kB SYS/USR stack */
+    0xd1, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd1   @ enter FIQ mode */
     0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
-    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048  @ 2kB FIQ stack */
-    0xd2, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd2  @ enter IRQ mode */
+    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048   @ 2kB FIQ stack */
+    0xd2, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd2   @ enter IRQ mode */
     0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
-    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048  @ 2kB IRQ stack */
-    0xd7, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd7  @ enter ABT mode */
+    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048   @ 2kB IRQ stack */
+    0xd7, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd7   @ enter ABT mode */
     0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
-    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048  @ 2kB ABT stack */
-    0xdb, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdb  @ enter UND mode */
+    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048   @ 2kB ABT stack */
+    0xdb, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdb   @ enter UND mode */
     0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
-    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048  @ 2kB UND stack */
-    0xd3, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd3  @ enter SVC mode */
-    0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0         @ 23kB left for SVC stack */
-    0xdf, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdf  @ enter SYS mode */
-    0x60, 0x00, 0x04, 0xe3, /* movw r0, #0x4060   @ r0 -> monitor vba */
-    0x01, 0x00, 0x44, 0xe3, /* movt r0, #0x4001 */
+    0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048   @ 2kB UND stack */
+    0xd3, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd3   @ enter SVC mode */
+    0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0          @ 23kB left for SVC stack */
+    0xdf, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdf   @ enter SYS mode */
+    0x40, 0x04, 0xa0, 0xe3, /* mov r0, #0x40000000 @ r0 -> vba */
+    0x05, 0x09, 0x80, 0xe2, /* add r0, r0, #0x14000 */
+    0x10, 0x0f, 0x0c, 0xfe, /* mcr2 p15, 0, r0, c12, c0, 0 */
+    0x60, 0x00, 0x80, 0xe2, /* add r0, r0, #0x60  @ r0 -> monitor vba */
     0x30, 0x0f, 0x0c, 0xfe, /* mcr2 p15, 0, r0, c12, c0, 1 */
     0x1c, 0x00, 0x40, 0xe2, /* sub r0, r0, #1c    @ r0 -> booting parameter struct */
     0x01, 0xf0, 0xa0, 0xe1, /* mov pc, r1 */
@@ -870,30 +872,38 @@ static int omap3_onenand_boot(struct omap_mpu_state_s *s)
     return result;
 }
 
+void omap3_boot_rom_init(struct omap_mpu_state_s *s)
+{
+    const uint8_t rom_version[4] = { 0x00, 0x14, 0x00, 0x00 }; /* v. 14.00 */
+
+    if (!s->bootrom_base) {
+        s->bootrom_base = qemu_ram_alloc(NULL, "omap3_boot_rom",
+                                         OMAP3XXX_BOOTROM_SIZE);
+        cpu_register_physical_memory(OMAP3_Q1_BASE + 0x14000,
+                                     OMAP3XXX_BOOTROM_SIZE,
+                                     s->bootrom_base | IO_MEM_ROM);
+        cpu_physical_memory_write_rom(OMAP3_Q1_BASE + 0x14000,
+                                      omap3_boot_rom,
+                                      sizeof(omap3_boot_rom));
+        cpu_physical_memory_write_rom(OMAP3_Q1_BASE + 0x1bffc,
+                                      rom_version,
+                                      sizeof(rom_version));
+        cpu_physical_memory_write(OMAP3_SRAM_BASE + 0xffc8,
+                                  omap3_sram_vectors,
+                                  sizeof(omap3_sram_vectors));
+    }
+}
 
 void omap3_boot_rom_emu(struct omap_mpu_state_s *s)
 {
-    const uint8_t rom_version[4] = { 0x00, 0x14, 0x00, 0x00 }; /* v. 14.00 */
     uint8_t x[4] = {0, 0, 0, 0};
     int result = 0;
     
+    /* only emulate the boot rom if it was initialized earlier */
     if (!s->bootrom_base) {
-        s->bootrom_base = qemu_ram_alloc(NULL, "omap3_boot_rom",
-                                         OMAP3XXX_BOOTROM_SIZE);
+        return;
     }
-    cpu_register_physical_memory(OMAP3_Q1_BASE + 0x14000,
-                                 OMAP3XXX_BOOTROM_SIZE,
-                                 s->bootrom_base | IO_MEM_ROM);
-    cpu_physical_memory_write_rom(OMAP3_Q1_BASE + 0x14000,
-                                  omap3_boot_rom,
-                                  sizeof(omap3_boot_rom));
-    cpu_physical_memory_write_rom(OMAP3_Q1_BASE + 0x1bffc,
-                                  rom_version,
-                                  sizeof(rom_version));
-    cpu_physical_memory_write(OMAP3_SRAM_BASE + 0xffc8,
-                              omap3_sram_vectors,
-                              sizeof(omap3_sram_vectors));
-
+    
     /* here we are relying on all memories to be attached and gpmc_attach
      * to fill in DEVICETYPE field correctly for CS0 for us */
     cpu_physical_memory_read(0x6e000060, x, 4); /* GPMC_CONFIG1_0 */
@@ -911,11 +921,10 @@ void omap3_boot_rom_emu(struct omap_mpu_state_s *s)
     /* if no boot loader found yet, try the MMC/SD card... */
     if (!result)
         result = omap3_mmc_boot(s);
-    
-    /* ensure boot ROM is mapped at zero address */
-    cpu_register_physical_memory(0, OMAP3XXX_BOOTROM_SIZE,
-                                 s->bootrom_base | IO_MEM_ROM);
-    
+
+    /* move PC to the boot ROM reset vector */
+    s->env->regs[15] = 0x40014000;
+
     if (!result) { /* no boot device found */
         /* move PC to the appropriate ROM dead loop address */
         s->env->regs[15] = 0x400140a4;