diff options
| author | Michael Davidsaver <mdavidsaver@gmail.com> | 2015-12-02 19:18:47 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-01-23 13:33:40 +0000 |
| commit | 48fa28e2864a90e89316fd2f01c6b847aa51c4d9 (patch) | |
| tree | f4b98d77877912c7e2f316ac3c6c7a13a91e0bde | |
| parent | b507f42855c2b3d1bb0d9264f232ebd30ab52da8 (diff) | |
armv7m: observable initial register state
At least for TI TM4C1294.
LR==-1
XPSR==0
PRIMASK, FAULTMASK, and BASEPRI all cleared
so exception handlers are unmasked.
STKALIGN set.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
| -rw-r--r-- | target/arm/cpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3a260f190c..a51874b951 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -189,7 +189,10 @@ static void arm_cpu_reset(CPUState *s) env->v7m.exception_prio = env->v7m.pending_prio = 0x100; - env->daif &= ~PSTATE_I; + env->v7m.ccr = 1<<9; /* STKALIGN */ + + env->daif &= ~(PSTATE_I|PSTATE_F); + env->ZF = 1; rom = rom_ptr(0); if (rom) { /* Address zero is covered by ROM which hasn't yet been @@ -208,6 +211,7 @@ static void arm_cpu_reset(CPUState *s) } env->regs[13] = initial_msp & 0xFFFFFFFC; + env->regs[14] = 0xffffffff; env->regs[15] = initial_pc & ~1; env->thumb = initial_pc & 1; } |