diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-05-08 08:21:52 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-12 14:10:05 +0100 |
| commit | c39e7595acd6d73b25f7ee02eb07e4e4408b115b (patch) | |
| tree | edd16ffed0a8e44b68708803506ed3cc5a42574f | |
| parent | 1e3ec56c6200cab94a8a39ca32d4e8a1cdfebd14 (diff) | |
target/arm: Swap argument order for VSHL during decode
Rather than perform the argument swap during code generation,
perform it during decode. This means it doesn't have to be
special cased later, and we can share code with aarch64 code
generation. Hopefully the decode comment addresses any confusion
that might arise in between.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200508152200.6547-9-richard.henderson@linaro.org
| -rw-r--r-- | target/arm/neon-dp.decode | 9 | ||||
| -rw-r--r-- | target/arm/translate-neon.inc.c | 3 |
2 files changed, 8 insertions, 4 deletions
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index ec3a92fe75..6b0b6566d6 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -65,8 +65,13 @@ VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same -VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same -VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same +# The shift operations are of the form Vd = Vm << Vn. +# By reversing the names of the fields here, we can use standard expanders. +@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \ + &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp + +VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev +VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index aefeff498a..416302bcc7 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -692,8 +692,7 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) uint32_t rn_ofs, uint32_t rm_ofs, \ uint32_t oprsz, uint32_t maxsz) \ { \ - /* Note the operation is vshl vd,vm,vn */ \ - tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \ oprsz, maxsz, &OPARRAY[vece]); \ } \ DO_3SAME(INSN, gen_##INSN##_3s) |