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authorPeter Maydell <peter.maydell@linaro.org>2016-01-14 12:54:40 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-01-14 12:54:40 +0000
commit98116aeb38d949e3c5884dbfdeb8c0b9dd91bcfb (patch)
tree132d86a64845891c020f16603a3939d3401e5f56
parent5af52c2f8156aba8b825472af07845cad988921a (diff)
downloadqemu-arm-98116aeb38d949e3c5884dbfdeb8c0b9dd91bcfb.tar.gz
cpu: Add new asidx_from_attrs() method
Add a new method to CPUClass which the memory system core can use to obtain the correct address space index to use for a memory access with a given set of transaction attributes, together with the wrapper function cpu_asidx_from_attrs() which implements the default behaviour ("always use asidx 0") for CPU classes which don't provide the method. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--include/qom/cpu.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 58605a5350..ed232463d5 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -102,6 +102,8 @@ struct TranslationBlock;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @debug_excp_handler: Callback for handling debug exceptions.
@@ -158,6 +160,7 @@ typedef struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
void (*debug_excp_handler)(CPUState *cpu);
@@ -492,6 +495,23 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
}
+
+/** cpu_asidx_from_attrs:
+ * @cpu: CPU
+ * @attrs: memory transaction attributes
+ *
+ * Returns the address space index specifying the CPU AddressSpace
+ * to use for a memory access with the given transaction attributes.
+ */
+static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->asidx_from_attrs) {
+ return cc->asidx_from_attrs(cpu, attrs);
+ }
+ return 0;
+}
#endif
/**