diff options
| author | Onur Sahin <onursahin08@gmail.com> | 2018-04-10 13:02:24 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-04-10 13:02:24 +0100 |
| commit | c4869ca630a57f4269bb932ec7f719cef5bc79b8 (patch) | |
| tree | 9873717c1546b9598a067009bd2a0cbe1e01d146 | |
| parent | 8720daad476fd9688b0c7e2453624c8a225c9c72 (diff) | |
target-arm: Check undefined opcodes for SWP in A32 decoder
Make sure we are not treating architecturally Undefined instructions
as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
We also choose to UNDEF for the architecturally UNPREDICTABLE case of
bits [11:8] not being zero.
Signed-off-by: Onur Sahin <onursahin08@gmail.com>
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index fc03b5b8c8..db1ce6510a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9237,11 +9237,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } tcg_temp_free_i32(addr); - } else { + } else if ((insn & 0x00300f00) == 0) { + /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx + * - SWP, SWPB + */ + TCGv taddr; TCGMemOp opc = s->be_data; - /* SWP instruction */ rm = (insn) & 0xf; if (insn & (1 << 22)) { @@ -9259,6 +9262,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) get_mem_index(s), opc); tcg_temp_free(taddr); store_reg(s, rd, tmp); + } else { + goto illegal_op; } } } else { |