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authorJiang Biao <jiang.biao2@zte.com.cn>2017-07-10 17:12:14 +0800
committerRichard Henderson <rth@twiddle.net>2017-07-19 14:45:15 -0700
commit4df9cac57f5220c17d856292e90fce455f708421 (patch)
tree51df804d124530f6a5a7bcb77813c853f5a04426
parentd4e59218ab80e86015753782fb5378767a51ccd0 (diff)
downloadqemu-arm-4df9cac57f5220c17d856292e90fce455f708421.tar.gz
tcg/mips: reserve a register for the guest_base.
Reserve a register for the guest_base using ppc code for reference. By doing so, we do not have to recompute it for every memory load. Signed-off-by: Jiang Biao <jiang.biao2@zte.com.cn> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1499677934-2249-1-git-send-email-jiang.biao2@zte.com.cn>
-rw-r--r--tcg/mips/tcg-target.inc.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 85756b81d5..1a8169f5fc 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -85,6 +85,10 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_TMP2 TCG_REG_T8
#define TCG_TMP3 TCG_REG_T7
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG TCG_REG_S1
+#endif
+
/* check if we really need so many registers :P */
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers. */
@@ -1547,8 +1551,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
@@ -1652,8 +1655,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
@@ -2452,6 +2454,13 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
+#ifndef CONFIG_SOFTMMU
+ if (guest_base) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
/* delay slot */