diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:45:39 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:43:52 +0100 |
| commit | 78011586b90d1d72bd14bacfdfcec1b4b9ab6114 (patch) | |
| tree | 2dd7181adfff0eddd951895ca1a3e9f25e2f84b8 | |
| parent | 4630353559fc1924c5f692aacb0d52e7e9ba5f5c (diff) | |
target/arm: Enable SME for user-only
Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-45-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b54443843..5de7e097e9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -210,6 +210,17 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } + /* and for SME instructions, with default vector length, and TPIDR2 */ + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.sctlr_el[1] |= SCTLR_EnTP2; + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, SMEN, 3); + env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; + if (cpu_isar_feature(aa64_sme_fa64, cpu)) { + env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], + SMCR, FA64, 1); + } + } /* * Enable 48-bit address space (TODO: take reserved_va into account). * Enable TBI0 but not TBI1. |