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authorAndreas Färber <afaerber@suse.de>2012-05-05 15:43:31 +0200
committerAndreas Färber <afaerber@suse.de>2012-06-04 23:00:45 +0200
commitb7e516ce04fecf260e7c0893b0afb3ff24a40358 (patch)
tree58ace85bf3626bc9738745d115591928638ac83f
parentff18b7625f5f36ac19b69ed5f0f946093a407174 (diff)
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--cpu-all.h1
-rw-r--r--target-arm/helper.c5
-rw-r--r--target-cris/translate.c5
-rw-r--r--target-i386/helper.c6
-rw-r--r--target-lm32/helper.c6
-rw-r--r--target-m68k/helper.c5
-rw-r--r--target-microblaze/translate.c5
-rw-r--r--target-mips/cpu.h3
-rw-r--r--target-ppc/helper.c5
-rw-r--r--target-s390x/helper.c9
-rw-r--r--target-sh4/translate.c5
-rw-r--r--target-sparc/cpu.c5
-rw-r--r--target-xtensa/helper.c5
13 files changed, 4 insertions, 61 deletions
diff --git a/cpu-all.h b/cpu-all.h
index 028528f0be..3a93c0c98a 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -443,7 +443,6 @@ void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
void cpu_single_step(CPUArchState *env, int enabled);
-void cpu_state_reset(CPUArchState *s);
int cpu_is_stopped(CPUArchState *env);
void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 06ebffcf53..bbb1d05d10 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4,11 +4,6 @@
#include "host-utils.h"
#include "sysemu.h"
-void cpu_state_reset(CPUARMState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
{
int nregs;
diff --git a/target-cris/translate.c b/target-cris/translate.c
index eed03d3d86..1ad9ec788e 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3576,11 +3576,6 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
return cpu;
}
-void cpu_state_reset(CPUCRISState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 8df109f7f6..2cc80977e8 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -26,12 +26,6 @@
//#define DEBUG_MMU
-/* NOTE: must be called outside the CPU execute loop */
-void cpu_state_reset(CPUX86State *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
static void cpu_x86_version(CPUX86State *env, int *family, int *model)
{
int cpuver = env->cpuid_version;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 3b1cee711e..1ea477fea3 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -233,9 +233,3 @@ void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
env->flags &= ~LM32_FLAG_IGNORE_MSB;
}
}
-
-void cpu_state_reset(CPULM32State *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f428375d7d..eac0053c5d 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -98,11 +98,6 @@ static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
return 0;
}
-void cpu_state_reset(CPUM68KState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
CPUM68KState *cpu_m68k_init(const char *cpu_model)
{
M68kCPU *cpu;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 3c2936f1b1..02b2dc6b96 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -2001,11 +2001,6 @@ MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
return cpu;
}
-void cpu_state_reset(CPUMBState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
{
env->sregs[SR_PC] = gen_opc_pc[pc_pos];
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index c7c9cb9a6a..ce3467f140 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -637,6 +637,9 @@ static inline CPUMIPSState *cpu_init(const char *cpu_model)
return &cpu->env;
}
+/* TODO QOM'ify CPU reset and remove */
+void cpu_state_reset(CPUMIPSState *s);
+
/* mips_timer.c */
uint32_t cpu_mips_get_random (CPUMIPSState *env);
uint32_t cpu_mips_get_count (CPUMIPSState *env);
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 42f66e8948..f556f8567a 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -3186,11 +3186,6 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
TARGET_FMT_lx "\n", RA, msr);
}
-void cpu_state_reset(CPUPPCState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
PowerPCCPU *cpu_ppc_init(const char *cpu_model)
{
PowerPCCPU *cpu;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 209a69603c..a34a35b536 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -106,14 +106,7 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw
return 1;
}
-#endif /* CONFIG_USER_ONLY */
-
-void cpu_state_reset(CPUS390XState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
-#ifndef CONFIG_USER_ONLY
+#else /* !CONFIG_USER_ONLY */
/* Ensure to exit the TB after this call! */
static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 7d35b84155..6532ad2ade 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -178,11 +178,6 @@ void cpu_dump_state(CPUSH4State * env, FILE * f,
}
}
-void cpu_state_reset(CPUSH4State *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
typedef struct {
const char *name;
int id;
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 8ccac23865..f7c004c7d8 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -23,11 +23,6 @@
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
-void cpu_state_reset(CPUSPARCState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
/* CPUClass::reset() */
static void sparc_cpu_reset(CPUState *s)
{
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index e6cb3fe91e..5e7e72e113 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -33,11 +33,6 @@
#include "hw/loader.h"
#endif
-void cpu_state_reset(CPUXtensaState *env)
-{
- cpu_reset(ENV_GET_CPU(env));
-}
-
static struct XtensaConfigList *xtensa_cores;
void xtensa_register_core(XtensaConfigList *node)