diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-18 18:56:15 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-19 17:38:48 +0100 |
| commit | 5b67106992e2a829119a7902925d6b79cab4ad14 (patch) | |
| tree | 8354f7ed2fa4aba4d98437d0c002acddb6f04e37 | |
| parent | 2d1a11783734e1fa04da1cd85b669314979b0cbe (diff) | |
target/arm: Remove writefn from TTBR0_EL3
The EL3 version of this register does not include an ASID,
and so the tlb_flush performed by vmsa_ttbr_write is not needed.
Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20181019015617.22583-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index bf4f50196d..20114bf574 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4312,7 +4312,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .access = PL3_RW, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, |