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author陳韋任 (Wei-Ren Chen) <chenwj@iis.sinica.edu.tw>2012-11-14 10:49:55 +0800
committerAurelien Jarno <aurelien@aurel32.net>2012-11-15 14:48:16 +0100
commit6801038bc52d61f81ac8a25fbe392f1bad982887 (patch)
treeeb11fc0be31e6f07b8dce5e8ce3994fd818e954d
parent68d001928b151a0c50f367c0bdca645b3d5e9ed3 (diff)
downloadqemu-arm-6801038bc52d61f81ac8a25fbe392f1bad982887.tar.gz
target-mips: fix wrong microMIPS opcode encoding
While reading microMIPS decoding, I found a possible wrong opcode encoding. According to [1] page 166, the bits 13..12 for MULTU is 0x01 rather than 0x00. Please review, thanks. [1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP Application-Specific Extension to the microMIPS32 Architecture Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r--target-mips/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f6fc0c27ae..01b48fa2a2 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -10385,7 +10385,7 @@ enum {
/* bits 13..12 for 0x32 */
MULT_ACC = 0x0,
- MULTU_ACC = 0x0,
+ MULTU_ACC = 0x1,
/* bits 15..12 for 0x2c */
SEB = 0x2,