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authorMeador Inge <meadori@codesourcery.com>2012-08-21 12:31:37 -0500
committerAurelien Jarno <aurelien@aurel32.net>2012-08-23 17:21:05 +0200
commit94159135cb59684853dcd45ff70d6dbc54a29209 (patch)
tree1c7907543924eb8d7188a5f460ec00bcba0db81a
parent58617a795c8067b2f9800cffce60f38707d3aa31 (diff)
downloadqemu-arm-94159135cb59684853dcd45ff70d6dbc54a29209.tar.gz
target-mips: Enable access to required RDHWR hardware registers
While running in the usermode emulator all of the required* MIPS32r2 RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Note that these registers are still enabled when the MIPS ISA is not release 2. This is OK since the Linux kernel emulates access to them when they are not available in hardware. * There is also the ULR register which is only recommended for full release 2 compliance. Incidentally, accessing this register in the current implementation works fine without flipping its access bit. Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r--target-mips/translate.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 47daf8574f..d643676e58 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12768,8 +12768,9 @@ void cpu_state_reset(CPUMIPSState *env)
#if defined(CONFIG_USER_ONLY)
env->hflags = MIPS_HFLAG_UM;
- /* Enable access to the SYNCI_Step register. */
- env->CP0_HWREna |= (1 << 1);
+ /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
+ hardware registers. */
+ env->CP0_HWREna |= 0x0000000F;
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
env->hflags |= MIPS_HFLAG_FPU;
}