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authorRichard Henderson <rth@twiddle.net>2012-03-30 13:16:36 -0400
committerAurelien Jarno <aurelien@aurel32.net>2012-08-27 12:17:39 +0200
commit05168674505153a641c7bfddb691d2eda11d13d1 (patch)
tree7e96376b28873f81db3c1bd0cd0231e6a204e5b1
parent13d24f49720a3e7b35a21222ef182c8513f139db (diff)
downloadqemu-arm-05168674505153a641c7bfddb691d2eda11d13d1.tar.gz
target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r--target-mips/translate.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d8129864ed..f740a08320 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
} else if (index == 0) {
gen_load_gpr(t0, base);
} else {
- gen_load_gpr(t0, index);
- gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
+ gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */