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authorRichard Henderson <rth@twiddle.net>2011-05-20 13:21:15 -0700
committerRichard Henderson <rth@anchor.twiddle.net>2011-05-31 10:18:05 -0700
commit508b43eaf3dd179363557bf68e911ddea637e58b (patch)
tree7b2c22681c515dc0a57f0179e61f14e11aefa661
parent8417845ee9dbb2881409bac75365099d17d1cc3d (diff)
downloadqemu-arm-508b43eaf3dd179363557bf68e911ddea637e58b.tar.gz
target-alpha: Merge HW_REI and HW_RET implementations.
Signed-off-by: Richard Henderson <rth@twiddle.net>
-rw-r--r--target-alpha/helper.h1
-rw-r--r--target-alpha/op_helper.c10
-rw-r--r--target-alpha/translate.c19
3 files changed, 8 insertions, 22 deletions
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index f4f693aaa1..de86ff220c 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -100,7 +100,6 @@ DEF_HELPER_1(ieee_input_cmp, i64, i64)
DEF_HELPER_1(ieee_input_s, i64, i64)
#if !defined (CONFIG_USER_ONLY)
-DEF_HELPER_0(hw_rei, void)
DEF_HELPER_1(hw_ret, void, i64)
DEF_HELPER_2(mfpr, i64, int, i64)
DEF_HELPER_2(mtpr, void, int, i64)
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index a90c7a6490..ea11cd2cc9 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -1156,22 +1156,12 @@ uint64_t helper_cvtqg (uint64_t a)
/* PALcode support special instructions */
#if !defined (CONFIG_USER_ONLY)
-void helper_hw_rei (void)
-{
- env->pc = env->ipr[IPR_EXC_ADDR] & ~3;
- env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
- env->intr_flag = 0;
- env->lock_addr = -1;
- /* XXX: re-enable interrupts and memory mapping */
-}
-
void helper_hw_ret (uint64_t a)
{
env->pc = a & ~3;
env->ipr[IPR_EXC_ADDR] = a & 1;
env->intr_flag = 0;
env->lock_addr = -1;
- /* XXX: re-enable interrupts and memory mapping */
}
uint64_t helper_mfpr (int iprn, uint64_t val)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 2c0b9c2e6f..2559814eeb 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2876,25 +2876,22 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
#endif
case 0x1E:
- /* HW_REI (PALcode) */
+ /* HW_RET (PALcode) */
#if defined (CONFIG_USER_ONLY)
goto invalid_opc;
#else
if (!ctx->pal_mode)
goto invalid_opc;
if (rb == 31) {
- /* "Old" alpha */
- gen_helper_hw_rei();
- } else {
- TCGv tmp;
-
- if (ra != 31) {
- tmp = tcg_temp_new();
- tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51));
- } else
- tmp = tcg_const_i64(((int64_t)insn << 51) >> 51);
+ /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
+ address from EXC_ADDR. This turns out to be useful for our
+ emulation PALcode, so continue to accept it. */
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, ipr[IPR_EXC_ADDR]));
gen_helper_hw_ret(tmp);
tcg_temp_free(tmp);
+ } else {
+ gen_helper_hw_ret(cpu_ir[rb]);
}
ret = EXIT_PC_UPDATED;
break;